Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 516
UG586 November 30, 2016
www.xilinx.com
Chapter 4
LPDDR2 SDRAM Memory Interface
Solution
Introduction
The Xilinx
®
7 series FPGAs Memory Interface Solutions (MIS) core is a combined
pre-engineered controller and physical layer (PHY) for interfacing 7 series FPGA user
designs to LPDDR2 SDRAM devices. This user guide provides information about using,
customizing, and simulating a LPDDR2 SDRAM interface core for 7 series FPGAs.
Features
Enhancements to the Xilinx 7 series FPGA memory interface solutions from the earlier
memory interface solution device families include:
• Higher performance.
• New hardware blocks used in the physical layer: PHASER_IN and PHASER_OUT, PHY
control block, and I/O FIFOs (see Core Architecture, page 575).
• Pinout rules changed due to the hardware blocks (see Design Guidelines, page 631).
• Controller and user interface operate at 1/2 of the memory clock frequency.
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