Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 354
UG586 November 30, 2016
www.xilinx.com
Chapter 2: QDR II+ Memory Interface Solution
Verifying the Simulation Using the Example Design
The example design generated by the MIG tool includes a simulation test bench and
parameter file based on memory selection in the MIG tool.
The Questa Advanced Simulator, Vivado Simulator, IES, and VCS simulation tools are used
for verification of MIG IP core at each software release. Script files to run simulations with
IES and VCS simulators are generated in MIG generated output. Simulations using Questa
Advanced Simulator and Vivado simulators can be done through Vivado Tcl Console
commands or in Vivado IDE.
IMPORTANT: Other simulation tools can be used for MIG IP core simulation but are not specifically
verified by Xilinx.
Simulation Flow Using IES and VCS Script Files
To run the simulation, go to this directory:
<project_dir>/<Component_Name>_ex/imports
For a project created with the name set as project_1 and the Component Name entered
in Vivado IDE as mig_7series_0, go to the directory as follows:
project_1/mig_7series_0_ex/imports
IES and VCS simulation scripts are meant to be executed only in Linux operating systems.
The ies_run.sh and vcs_run.sh files are the executable files for running simulations
using IES and VCS simulators respectively. Library files should be added to the
ies_run.sh and vcs_run.sh files respectively. See the readme.txt file for details
regarding simulations using IES and VCS.
Simulation Flow Using Vivado Simulator
1. In the Open IP Example Design Vivado project, under Flow Navigator, select
Simulation Settings (Figure 2-50).
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English