Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 570
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
3. In the Flow Navigator window, select Run Simulation and select Run Behavioral
Simulation as shown in Figure 4-40.
Simulation Flow Using Questa Advanced Simulator
1. In the Open IP Example Design Vivado project, under Flow Navigator select
Simulation Settings.
2. Select Target simulator as Questa Advanced Simulator/ModelSim.
a. Browse to the Compiled libraries location and set the path on Compiled libraries
location option.
b. Under the Simulation tab, set the modelsim.simulate.runtime to 1 ms (there
are simulation RTL directives which stop the simulation after certain period of time,
which is less than 1 ms), set modelsim.simulate.vsim.more_options to
-novopt as shown in Figure 4-39.
3. Apply the settings and select OK.
X-Ref Target - Figure 4-40
Figure 4-40: Run Behavioral Simulation
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Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V