Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 332
UG586 November 30, 2016
www.xilinx.com
Chapter 2: QDR II+ Memory Interface Solution
The OSERDES is used to clock all outputs from the PHY to the memory device. Upon exiting
the OSERDES, all the output signals must be presented center aligned with respect to the
generated clocks K/K#. For this reason, the PHASER_OUT block is also used in conjunction
with the OSERDES to achieve center alignment. The output clocks that drive the address,
and controls are shifted such that the output signals are center aligned to the K/K# clocks
at the memory.
Read Path
The read path includes data capture using the memory provided read clocks and also
ensuring that the read clock is centered within the data window to ensure that good margin
is available during data capture. Before any read can take place, calibration must occur.
Calibration is the main function of the read path and needs to be performed before the user
interface can start transactions to the memory.
Data Capture
Figure 2-46 shows a high-level block diagram of the path the read clock and the read data
take from entering the FPGA until given to you. The read clock bypasses the ILOGIC and is
routed through PHASERs within each byte group through multi-region BUFMRs. The
BUFMR output can drive the PHASEREFCLK inputs of PHASERs in the immediate bank and
also the PHASERs available in the bank above and below the current bank. The PHASER
generated byte group clocks (ICLK, OCLK, and ICLKDIV) are then used to capture the read
data (Q) available within the byte group using the ISERDES block. The calibration logic
makes use of the fine delay increments available through the PHASER to ensure the byte
group clocks are centered inside the read data window, ensuring maximum data capture
margin.
The IN_FIFOs available in each byte group shown in Figure 2-46 receive 4-bit data from
each Q bit captured in the ISERDES in a given byte group and writes them into the storage
array. The half-frequency PHASER_IN generated byte group clock, ICLKDIV, that captures
the data in the ISERDES is also used to write the captured read data to the IN_FIFO. The
write enables to the IN_FIFO are always asserted to enable data to be written in
continuously.
A shallow, synchronous POST_FIFO is used at the receiving side of the IN_FIFO to enable
captured data to be read out continuously from the FPGA logic, should a flag assertion
occur in the IN_FIFO, which could potentially stall the flow of data from the IN_FIFO.
Calibration also ensures that the read data is aligned to the rising edge of the FPGA logic
half-frequency clock and that read data from all the byte groups have the same delay. For
more details about the actual calibration and alignment logic, see the Calibration section.
Send Feedback

Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English