Xilinx Zynq-7000

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 134
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Memory Initialization and Calibration Sequence
After deassertion of system reset, the PHY performs the required power-on initialization
sequence for the memory. This is followed by several stages of timing calibration for both
the write and read datapaths. After calibration is complete, the PHY indicates that
initialization is finished, and the controller can begin issuing commands to the memory.
Figure 1-57 shows the overall flow of memory initialization and the different stages of
calibration.
X-Ref Target - Figure 1-57
Figure 1-57: PHY Overall Initialization and Calibration Sequence
3YSTEM2ESET
$$2$$23$2!-)NITIALIZATION
0HASER?).0HASE,OCK0HASELOCKS2EAD$13TOINTERNALFREERUNNING
&REQUENCY2EFERENCECLOCK
0HASER?)N$13&/5.$CALIBRATION
2EAD,EVELING)NITIAL$1ALIGNMENTTO$13AND$13CENTERINGINREAD$1
WINDOW
7RITE#ALIBRATION!LIGNINGWRITE$13TOTHECORRECT#+#+EDGE
7RITE,EVELING&OR$$23$2!-/NLY
0(9)NITIALIZATIONAND#ALIBRATION#OMPLETE
-02-ULTI0URPOSE2EGISTER2EAD,EVELING#ENTER2EAD$13IN2EAD$1
WINDOWINDEPENDENTOFWRITES
/#,+$%,!9%$#ALIBRATION#ENTER7RITE$13IN7RITE$1WINDOWUSING
0HASER?/UT3TAGEDELAY
"ACKTOWRITELEVELINGTO
ADDTOT#+OFDELAY
TOHANDLEEARLYWRITES
7RITELEVELAGAIN
ATTHEENDOF
/#,+$%,!9%$
CALIBRATION
02"32EAD,EVELING2EAD$13CENTERINGINREAD$1WINDOWWITH02"3
PATTERNTOACCOUNTFOR)3)EFFECTS
8
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