Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 653
UG586 November 30, 2016
www.xilinx.com
Chapter 5: Multicontroller Design
13. Select MIG 7 Series to open the MIG tool (Figure 5-13).
Customizing and Generating the Core
CAUTION! The Windows operating system has a 260-character limit for path lengths, which can affect
the Vivado tools. To avoid this issue, use the shortest possible names and directory locations when
creating projects, defining IP or managed IP projects, and creating block designs.
Multiple Controllers
Select the number of controllers from the MIG Output Options page (Figure 5-14). The
number of controllers that can be accommodated varies based on the number of banks
available in the device and depends on the memory interface configuration chosen (that is,
the selected data width and number of banks).
X-Ref Target - Figure 5-13
Figure 5-13: 7 Series FPGAs Memory Interface Generator FPGA Front Page
Send Feedback

Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English