Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 101
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Write Priority (WRITE_PRIORITY, WRITE_PRIORITY_REG)
Write address channel is always given priority in this mode. The requests from the read
address channel are processed when there are no pending requests from the write address
channel. Arbitration outputs are registered in WRITE_PRIORITY_REG mode.
AXI4-Lite Slave Control/Status Register Interface Block
The AXI4-Lite Slave Control register block provides a processor accessible interface to the
ECC memory option. The interface is available when ECC is enabled and the primary slave
interface is AXI4. The block provides interrupts, interrupt enable, ECC status, ECC
enable/disable, ECC correctable errors counter, first failing correctable/uncorrectable data,
ECC and address. Fault injection registers for software testing is provided when the
ECC_TEST_FI_XOR (C_ECC_TEST) parameter is “ON.” The AXI4-Lite interface is fixed at 32
data bits and signaling follows the standard AMBA AXI4-Lite specifications [Ref 4].
The AXI4-Lite control/status register interface block is implemented in parallel to the AXI4
memory-mapped interface. The block monitors the output of the native interface to
capture correctable (single bit) and uncorrectable (multiple bit) errors. When a correctable
and/or uncorrectable error occurs, the interface also captures the byte address of the failure
along with the failing data bits and ECC bits. Fault injection is provided by an XOR block
placed in the write datapath after the ECC encoding has occurred. Only the first memory
beat in a transaction can have errors inserted. For example, in a memory configuration with
a data width of 72 and a mode register set to burst length 8, only the first 72 bits are
corruptible through the fault injection interface. Interrupt generation based on either a
correctable or uncorrectable error can be independently configured with the register
interface.
ECC Enable/Disable
The ECC_ON_OFF register enables/disables the ECC decode functionality. However,
encoding is always enabled. The default value at start-up can be parameterized with
C_ECC_ONOFF_RESET_VALUE. Assigning a value of 1 for the ECC_ON_OFF bit of this register
results in the correct_en signal input into the mem_intfc to be asserted. Writing a value
of 0 to the ECC_ON_OFF bit of this register results in the correct_en signal to be
deasserted. When correct_en is asserted, decoding is enabled, and the opposite is true
when this signal is deasserted. ECC_STATUS/ECC_CE_CNT are not updated when
ECC_ON_OFF = 0. The FI_D0, FI_D1, FI_D2, and FI_D3 registers are not writable when
ECC_ON_OFF = 0.
Single Error and Double Error Reporting
Two vectored signals from the Memory Controller indicate an ECC error: ecc_single and
ecc_multiple. The ecc_single signal indicates if there has been a correctable error,
and the ecc_multiple signal indicates if there has been an uncorrectable error. The
widths of ecc_multiple and ecc_single are based on the C_NCK_PER_CLK parameter.
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