Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 107
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
CE_FFA[31:0]
This register stores the address (Bits[31:0]) of the first occurrence of an access with a
correctable error. When the CE_STATUS bit in the ECC Status register is cleared, this register
is re-enabled to store the address of the next correctable error. Storing of the failing address
is enabled after reset.
CE_FFA[63:32]
Note: This register is unused if C_S_AXI_ADDR_WIDTH < 33.
This register stores the address (Bits[63:32]) of the first occurrence of an access with a
correctable error. When the CE_STATUS bit in the ECC Status register is cleared, this register
is re-enabled to store the address of the next correctable error. Storing of the failing address
is enabled after reset.
CE_FFD[31:0]
This register stores the (corrected) failing data (Bits[31:0]) of the first occurrence of an
access with a correctable error. When the CE_STATUS bit in the ECC Status register is cleared,
this register is re-enabled to store the data of the next correctable error. Storing of the
failing data is enabled after reset.
CE_FFD[63:32]
This register stores the (corrected) failing data (Bits[63:32]) of the first occurrence of an
access with a correctable error. When the CE_STATUS bit in the ECC Status register is cleared,
Table 1-28: Correctable Error First Failing Address [31:0] Register Bit Definitions
Bits Name Core Access Reset Value Description
31:0 CE_FFA[31:0] R 0
Address (Bits[31:0]) of the first occurrence of a
correctable error
Table 1-29: Correctable Error First Failing Address [63:32] Register Bit Definitions
Bits Name Core Access Reset Value Description
31:0 CE_FFA[63:32] R 0
Address (Bits[63:32]) of the first occurrence of a
correctable error.
Table 1-30: Correctable Error First Failing Data [31:0] Register Bit Definitions
Bits Name Core Access Reset Value Description
31:0 CE_FFD[31:0] R 0
Data (Bits[31:0]) of the first occurrence of a
correctable error.
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Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V