Xilinx Zynq-7000

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 317
UG586 November 30, 2016
www.xilinx.com
Chapter 2: QDR II+ Memory Interface Solution
Core Architecture
Overview
Figure 2-38 shows a high-level block diagram of the 7 series FPGA QDR II+ SRAM interface
solution. This figure shows both the internal FPGA connections to the client interface for
initiating read and write commands, and the external interface to the memory device.
X-Ref Target - Figure 2-38
Figure 2-38: High-Level Block Diagram of QDR II+ Interface Solution
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