Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 318
UG586 November 30, 2016
www.xilinx.com
Chapter 2: QDR II+ Memory Interface Solution
The PHY is composed of these elements, as shown in Figure 2-39:
• User interface
• Physical interface
a. Write path
b. Read datapath
X-Ref Target - Figure 2-39
Figure 2-39: Components of the QDR II+ SRAM Memory Interface Solution
Reset
Module
Read Path
Write Path
Clock
Generation
UG586_c2_35_090911
Client Interface
User
Device
Physical Interface
clk_wr
ck_mem
clk
sys_rst
qdr_k_p
qdr_k_n
rst_dk
mmcm_locked
iodelay_ctrl_rdy
app_wr_cmd
app_rd_cmd
app_wr_addr
app_rd_addr
app_wr_data
app_wr_bw_n
app_rd_valid
init_calib_complete
app_rd_data
QDR II+ SRAM
Device
phy_top
user_top
qdr_w_n
qdr_r_n
qdr_sa
qdr_d
qdr_bw_n
qdr_cq_p
qdr_cq_n
qdr_q
qdr_dll_off_n
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Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V