Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 208
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
source can be connected directly to the DIFF_SSTL18_II CCIO pins. For more details on
usage and required circuitry for LVDS and LVDS_25 I/O Standards, see the 7 Series FPGAs
SelectIO™ Resources User Guide (UG471) [Ref 2].
Termination
These rules apply to termination for DDR2 SDRAM:
• Simulation (using IBIS or other) is highly recommended. The loading of address (A, BA),
command (RAS_N, CAS_N, WE_N), and control (CS_N, ODT) signals depends on
various factors, such as speed requirements, termination topology, use of unbuffered
DIMMs, and multiple rank DIMMs. Loading can be a limiting factor in reaching a
performance target.
• Unidirectional signals should be terminated with the memory device internal
termination or a pull-up of 50Ω to VTT at the load (Figure 1-91 with 50Ω instead of
40Ω). A split 100Ω termination to V
CCO
and a 100Ω termination to GND can be used
(Figure 1-92 with 100Ω instead of 80Ω), but takes more power. For bidirectional
signals, the termination is needed at both ends of the signal. ODT should be used on
the memory side. For best performance in HP banks, DCI should be used. For best
performance in HR banks, IN_TERM (internal termination) should be used.
• Differential signals should be terminated with the memory device internal termination
or a 100Ω differential termination at the load (Figure 1-93). For bidirectional signals,
termination is needed at both ends of the signal. ODT should be used on the memory
side. For best performance in HP banks, DCI should be used. For best performance in
HR banks, IN_TERM (internal termination) should be used.
• All termination must be placed as close to the load as possible. The termination can be
placed before or after the load provided that the termination is placed within a small
distance of the load pin. The allowable distance can be determined by simulation.
• DCI (HP banks) or IN_TERM (HR banks) is required at the FPGA to meet the specified
performance.
• Address (A, BA) and control signals (RAS_N, CAS_N, WE_N, CS_N, ODT) are to be
terminated with the onboard DIMM termination. If DIMM termination does not exist or
a component is being used, a 50Ω pull-up to V
TT
at the far end of the line should be
used except for the CK/CK_N which requires a differential termination.
•The CKE signal is not terminated. This signal should be pulled down during memory
initialization with a 4.7 kΩ resistor connected to GND.
• ODT, which terminates a signal at the memory, is required. The MIG tool should be used
to specify the configuration of the memory system for setting the mode register
properly. See Micron technical note TN-47-01 [Ref 14] for additional details on ODT.
• ODT applies to the DQ, DQS, and DM signals only. If ODT is used, the mode register must
be set appropriately to enable ODT at the memory.
Send Feedback

Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English