Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 207
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
These signals are all set to LVCMOS25 and can be altered as needed for the system design.
They can be generated and used internally instead of being brought out to pins.
A 16-bit wide interface might need to have the system clock in a bank above or below the
bank with the address/control and data. In this case, the MIG tool puts an additional
constraint in the XDC. An example is shown here:
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sys_clk_p]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hierarchical *pll*CLKIN1]
This results in a warning listed below during PAR. This warning can be ignored.
WARNING:Place:1402 - A clock IOB/PLL clock component pair have been found that are
not placed at an optimal clock IOB/PLL site pair. The clock IOB component <sys_clk_p> is
placed at site <IOB_X1Y76>. The corresponding PLL component
<u_backb16/u_ddr2_infrastructure/plle2_i> is placed at site <PLLE2_ADV_X1Y2>. The
clock I/O can use the fast path between the IOB and the PLL if the IOB is placed on a Clock
Capable IOB site that has dedicated fast path to PLL sites within the same clock region.
You might want to analyze why this issue exists and correct it. This is normally an ERROR
but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN
<sys_clk_p.PAD> allowing your design to continue. This constraint disables all clock
placer rules related to the specified COMP.PIN. The use of this override is highly
discouraged as it might lead to very poor timing results. It is recommended that this error
condition be corrected in the design.
Do not drive user clocks through the I/O clocking backbone from the region(s) containing
the MIG generated memory interface to CMT blocks in adjacent regions due to resource
limitations. For more information, see the 7 Series FPGAs Clocking Resources User Guide
(UG472) [Ref 10].
The MIG tool sets the VCCAUX_IO constraint based on the data rate and voltage input
selected. The generated XDC has additional constraints as needed. For example:
# PadFunction: IO_L14P_T2_SRCC_36
set_property VCCAUX_IO NORMAL [get_ports {ddr2_dq[0]}]
set_property SLEW FAST [get_ports {ddr2_dq[0]}]
set_property IOSTANDARD SSTL18_II_T_DCI [get_ports {ddr2_dq[0]}]
set_property PACKAGE_PIN AJ12 [get_ports {ddr2_dq[0]}]
# PadFunction: IO_L14N_T2_SRCC_36
set_property VCCAUX_IO NORMAL [get_ports {ddr2_dq[1]}]
set_property SLEW FAST [get_ports {ddr2_dq[1]}]
set_property IOSTANDARD SSTL18_II_T_DCI [get_ports {ddr2_dq[1]}]
set_property PACKAGE_PIN AK12 [get_ports {ddr2_dq[1]}]
Consult the Xilinx Timing Constraints User Guide (UG612) [Ref 15] for more information.
For DDR2 SDRAM interfaces that have the memory system input clock
(sys_clk_p/sys_clk_n) placed on CCIO pins within one of the memory banks, MIG
assigns the DIFF_SSTL18_II I/O standard (VCCO = 1.8V) to the CCIO pins. Because the same
differential input receiver is used for both DIFF_SSTL18_II and LVDS inputs, an LVDS clock
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English