Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 375
UG586 November 30, 2016
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Chapter 2: QDR II+ Memory Interface Solution
Read Stage 1 Calibration Debug Signals
Table 2-20 indicates the mapping between bits within the dbg_rd_stage1_cal bus and
debug signals in the PHY. All signals are found within the qdr_rld_phy_rdlvl module
and are all valid in the clk domain.
dbg_wr_init[36:33] seen_valid_r Successful read level recorded per lane.
dbg_wr_init[37] qdr_edge_adv_err Edge advance timeout.
dbg_wr_init[38] qdr_stg2_err Latency calibration timeout.
dbg_wr_init[39] rst_samp_cnt Reset sample counters.
Table 2-19: Write Init Debug Signal Map (Cont’d)
Bits PHY Signal Name Description
Table 2-20: Read Stage 1 Debug Signal Map
Bits PHY Signal Name Description
dbg_rd_stage1_cal[2:0] sm_r Read level main state machine.
dbg_rd_stage1_cal[7:6] seq_sm_r Read level sequence state bits.
dbg_rd_stage1_cal[14:12] rdlvl_work_lane_r Lane currently undergoing read level calibration.
dbg_rd_stage1_cal[15] rdlvl_stg1_start Write side signal causing read level block to start.
dbg_rd_stage1_cal[16] rdlvl_stg1_done Read level block signals completion.
dbg_rd_stage1_cal[17] rdlvl_stg1_start
Write side signal causing read level to copy first lane
result across all lanes.
dbg_rd_stage1_cal[25:18] rdlvl_stg1_cal_bytes_r Lanes for which write side is requesting calibration.
dbg_rd_stage1_cal[31] cmplx_rdcal_start Write side signal causing read level to do complex cal.
dbg_rd_stage1_cal[32] cmplx_rd_data_valid
Write side signal informing read level that complex read
data is valid.
dbg_rd_stage1_cal[48:41] rd_data_comp_r Per byte comparison results for complex calibration.
dbg_rd_stage1_cal[56:49] iserdes_comp_r Per byte comparison results for simple calibration.
dbg_rd_stage1_cal[57] rdlvl_lane_match Overall comparison result for both simple and complex.
dbg_rd_stage1_cal[66:61] largest_left_edge Phaser in taps when the right most left edge was found.
dbg_rd_stage1_cal[72:67] smallest_right_edge Phaser in taps when the left most right edge was found.
dbg_rd_stage1_cal[78:73] mem_out_dec Output of static compensation ROM.
dbg_rd_stage1_cal[81] rdlvl_pi_stg2_f_incdec Controls directing of phaser in stepping.
dbg_rd_stage1_cal[82] rdlvl_pi_en_stg2_f Phaser in step command.
dbg_rd_stage1_cal[85:83] pi_lane_r Lane to which phaser in commands apply.
dbg_rd_stage1_cal[91] prev_match_r Previous sample matched.
dbg_rd_stage1_cal[96:92] match_out_r idelay of last detected invalid to valid match transition.
dbg_rd_stage1_cal[102:97] samp_cnt_r Sample counter.
dbg_rd_stage1_cal[108:103] samps_match_r Cumulative sample match count.
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