Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 121
UG586 November 30, 2016
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Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Write Path (Output) I/O Logic Clock
The output path comprising both data and controls is clocked by PHASER_OUT. The
PHASER_OUT provides synchronized clocks for each byte group to the OUT_FIFOs and to
the OSERDES/ODDR. The PHASER_OUT generates a byte clock (OCLK), a divided byte clock
(OCLKDIV), and a delayed byte clock (OCLK_DELAYED) for its associated byte group. These
clocks are generated directly from the Frequency Reference clock and are in phase with
each other. The byte clock is the same frequency as the Frequency Reference clock and the
divided byte clock is half the frequency of the Frequency Reference clock. OCLK_DELAYED is
used to clock the DQS ODDR to achieve the required 90° phase offset between the write DQS
and its associated DQ bits. The PHASER_OUT also drives the signaling required to generate
DQS during writes, the DQS and DQ 3-state associated with the data byte group, and the
Read Enable for the OUT_FIFO of the byte group. The clocking details of the address/control
and the write paths using PHASER_OUT are shown in Figure 1-58 and Figure 1-60.
Read Path (Input) I/O Logic Clock
The input read datapath is clocked by the PHASER_IN block. The PHASER_IN block provides
synchronized clocks for each byte group to the IN_FIFOs and to the IDDR/ISERDES. The
PHASER_IN block receives the DQS signal for the associated byte group and generates two
delayed clocks for DDR2 or DDR3 SDRAM data captures: read byte clock (ICLK) and read
divided byte clock (ICLKDIV). ICLK is the delayed version of the frequency reference clock
that is phase-aligned with its associated DQS. ICLKDIV is used to capture data into the first
rank of flip-flops in the ISERDES. ICLKDIV is aligned to ICLK and is the parallel transfer clock
for the last rank of flip-flops in the ISERDES. ICLKDIV is also used as the write clock for the
IN_FIFO associated with the byte group. The PHASER_IN block also drives the write enable
(WrEnable) for the IN_FIFO of the byte group. The clocking details of the read path using
PHASER_IN is shown in Figure 1-60.
IDELAY Reference Clock
You need to always supply a 200 MHz ref_clk and then MIG creates the appropriate
IDELAYCTRL frequency with an additional MMCM. The IDELAYCTRL module continuously
calibrates the IDELAY elements in the I/O region to account for varying environmental
conditions. The IP core assumes an external clock signal is driving the IDELAYCTRL module.
If a PLL clock drives the IDELAYCTRL input clock, the PLL lock signal needs to be
incorporated in the rst_tmp_idelay signal inside the IODELAY_CTRL.v module. This
ensures that the clock is stable before being used.
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