Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 20
UG586 November 30, 2016
www.xilinx.com
Chapter 1
DDR3 and DDR2 SDRAM Memory
Interface Solution
Introduction
The Xilinx
®
7 series FPGAs Memory Interface Solutions (MIS) core is a combined
pre-engineered controller and physical layer (PHY) for interfacing 7 series FPGA user
designs and AMBA
®
Advanced eXtensible Interface (AXI4) slave interfaces to DDR3 and
DDR2 SDRAM devices. This user guide provides information about using, customizing, and
simulating a LogiCORE™ IP DDR3 or DDR2 SDRAM interface core for 7 series FPGAs. The
user guide describes the core architecture and provides details on customizing and
interfacing to the core.
IMPORTANT: Memory Interface Solutions v4.1 only supports the Vivado
®
Design Suite. The ISE
®
Design Suite is not supported in this version.
Features
Enhancements to the Xilinx 7 series FPGA memory interface solutions from earlier memory
interface solution device families include:
• Higher performance.
• New hardware blocks used in the physical layer: PHASER_IN and PHASER_OUT, PHY
control block, and I/O FIFOs (see Core Architecture, page 90).
• Pinout rules changed due to the hardware blocks (see Design Guidelines, page 192).
• Controller and user interface operate at 1/4 the memory clock frequency.
For a full list of supported features, see the Zynq-7000 AP SoC and 7 Series FPGAs Memory
Interface Solutions Data Sheet (DS176) [Ref 1].
Send Feedback

Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English