Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 402
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Finish
After the design is generated, a README page is displayed with additional useful
information.
Click Close to complete the MIG tool flow.
Vivado Integrated Design Flow for MIG
1. After clicking Generate, the Generate Output Products window appears. This window
has the Out-of-Context Settings as shown in Figure 3-25.
X-Ref Target - Figure 3-25
Figure 3-25: Generate Output Products Window
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