Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 274
UG586 November 30, 2016
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Chapter 2
QDR II+ Memory Interface Solution
Introduction
The QDR II+ SRAM Memory Interface Solution (MIS) is a physical layer for interfacing
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7 series FPGAs user designs to QDR II+ SRAM devices. QDR II+ SRAM capabilities
offer high-speed data transfers on separate read and write buses on the rising and falling
edges of the clock. These memory devices are used in high-performance systems as
temporary data storage, such as:
• Look-up tables in networking systems
• Packet buffers in network switches
• Cache memory in high-speed computing
• Data buffers in high-performance testers
The QDR II+ SRAM memory solutions core is a PHY that takes simple user commands,
converts them to the QDR II+ protocol, and provides the converted commands to the
memory. The PHY half-frequency design enables you to provide one read and one write
request per cycle eliminating the need for a Memory Controller and the associated
overhead, thereby reducing the latency through the core. Unique capabilities of the 7 series
FPGAs allow the PHY to maximize performance and simplify read data capture within the
FPGA. The full solution is complete with a synthesizable reference design.
This chapter describes the core architecture and information about using, customizing, and
simulating a LogiCORE™ IP QDR II+ SRAM MIS core for the 7 series FPGAs. Although this
soft Memory Controller core is a fully verified solution with guaranteed performance,
termination and trace routing rules for the PCB design need to be followed to have the best
possible solution. For detailed board design guidelines, see Design Guidelines, page 342.
IMPORTANT: QDR II+ SRAM designs currently do not support memory-mapped AXI4 interfaces.
For detailed information and updates about the 7 series FPGAs QDR II+ SRAM MIS core,
see the Xilinx 7Series FPGA Data Sheets [Ref 13] and the Zynq-7000 AP SoC and 7 Series
FPGAs Memory Interface Solutions Data Sheet (DS176) [Ref 1].