Xilinx Zynq-7000 - Page 316

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 316
UG586 November 30, 2016
www.xilinx.com
Chapter 2: QDR II+ Memory Interface Solution
• Verified system pin rules:
°
System clock:
- These pins should be allocated to either SR/MR CC I/O pair.
- These pins must be allocated in the Memory banks column.
- If the selected system clock type is single-ended, you need to check whether the
reference voltage pins are unallocated in the bank or the internal V
REF
is used.
°
Reference clock:
- These pins should be allocated to either SR/MR CC I/O pair.
- If the selected system clock type is single-ended, you need to check whether the
reference voltage pins are unallocated in the bank or the internal V
REF
is used.
°
Status signals:
-The sys_rst signal should be allocated in the bank where the V
REF
I/O is
unallocated or the internal V
REF
is used.
- These signals should be allocated in the non-memory banks because the I/O
standard is not compatible. The I/O standard type should be LVCMOS with the
I/O voltage at 1.8V.
- These signals can be allocated in any of the columns (there is no hard
requirement because these signals should reside in a memory column); however,
it is better to allocate closer to the chosen memory banks.
Send Feedback