Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 315
UG586 November 30, 2016
www.xilinx.com
Chapter 2: QDR II+ Memory Interface Solution
°
Interface banks should reside in the same column of the FPGA.
°
Interface banks should be either High Performance (HP) or High Range (HR). HP
banks are used for the high frequencies.
°
The chosen interface banks should have the same SLR region if the chosen device is
of stacked silicon interconnect technology.
°
V
REF
I/Os should be used as GPIOs when an internal V
REF
is used or if there are no
inout and input ports in a bank.
°
The I/O standard of each signal is verified as per the configuration chosen.
°
The VCCAUX I/O of each signal is verified and provides a warning message if the
provided VCCAUX I/O is not valid.
• Verified data read pin rules:
°
Pins related to one component should be allocated in one bank only.
°
The strobe pair (CQ) should be allocated to either the MRCC P or the MRCC N pin.
°
Read data pins cannot span more than the required byte lanes. For example, an
18-bit component should occupy only two byte lanes.
°
A byte lane should contain pins of only one read byte, for example, Q[8:0] or
Q[17:9].
°
A byte lane should not contain pins of more than one component.
°
An FPGA byte lane should not contain pins related to two different strobe sets.
°
V
REF
I/O can be used only when the internal V
REF
is chosen.
• Verified data write pin rules:
°
Pins related to one component should be allocated in only one bank.
°
Write clocks (K/K#) pairs should be allocated to the DQS CC I/Os.
°
Write data pins cannot span more than the required byte lanes. For example, an
18-bit component should occupy only 2 byte lanes.
°
A byte lane should not contain pins of more than one component.
°
A byte lane should contain pins of only one write byte, for example, D[8:0] or
D[17:9].
°
Irrespective of internal V
REF
usage, V
REF
pins can be used as GPIOs unless the bank
contains other input signals.
• Verified address pin rules:
°
Address signals cannot mix with data bytes except for the qdriip_dll_off_n
signal.
°
It can use any number of isolated byte lanes.
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Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V