Xilinx Zynq-7000

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 38
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
X-Ref Target - Figure 1-20
Figure 1-20: Setting AXI Parameter Options
UG586_c1_22_090511
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