Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 256
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
c. Using high quality scope and probes, verify the expected pattern
(FF00AA5555AA9966) is being written to the DRAM during a write and that the
expected pattern is being read back during the first Write Calibration read. If the
pattern is correct during write and read at the DRAM, verify the DQS-CK alignment.
During Write Calibration, these two signals should be aligned. Write Leveling aligned
these two signals which has successfully completed before Write Calibration.
d. Probe ODT and WE_N during a write command. In order for ODT to be properly
turned on in the memory, ODT must assert before the write command.
e. Probe DM to ensure it is held Low during calibration. If a board issue exists causing
DM to improperly assert, incorrect data is read back during calibration causing a
write calibration failure. An example of a board issue on DM is when DM is not used
and tied Low at the memory with improper termination.
5. It is possible for write calibration to fail due to rare manufacturing issues with the
memory device. Verify SDRAM pins are behaving correctly. Look for floating or
grounded signals. The debug signals should be used to determine which byte group is
failing and if specific pin(s) within that byte group are causing the incorrect data
pattern. These pins should be the focus at the memory device.
6. If the DQS-to-DQ, CWL, and DQS-to-CK look correct, review the above Debugging MPR
Read Leveling Failures – DDR3 Only (dbg_rdlvl_err[1] = 1) section.
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