Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 643
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
set. LPDDR2 SDRAM manages these constraints for designs generated with the System
Clock option selected as Differential/Single-Ended (at FPGA Options > System Clock).
If the design is generated with the System Clock option selected as No Buffer (at FPGA
Options > System Clock), the CLOCK_DEDICATED_ROUTE constraints based on
SRCC/MRCC I/O and MMCM allocation needs to be handled manually for the IP flow.
LPDDR2 SDRAM does not generate clock constraints in the XDC file for the No Buffer
configurations. You must take care of the clock constraints for the No Buffer configurations
in the IP flow.
Send Feedback

Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English