Xilinx Zynq-7000

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 288
UG586 November 30, 2016
www.xilinx.com
Chapter 2: QDR II+ Memory Interface Solution
QDR II+ SRAM designs do not support memory-mapped AXI4 interfaces.
X-Ref Target - Figure 2-16
Figure 2-16: Memory Selection Page
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