Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 155
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
A PHASER_IN provides two clock outputs namely ICLK and ICLKDIV. ICLK is the stage 2
delay output and ICLKDIV is the rising edge aligned divided by 2 version of ICLK.
The ICLK and ICLKDIV outputs of one PHASER_IN block are used to clock all the DQ
ISERDES associated with one byte. The ICLKDIV is also the write clock for the read DQ
IN_FIFOs. One PHASER_IN block is associated with a group of 12 I/Os. Each I/O bank in the
7 series FPGA has four PHASER_IN blocks, and hence four bytes for DDR2 or DDR3 SDRAM
can be placed in a bank.
Implementation Details
This stage of read leveling is performed one byte at a time where each DQS is center aligned
to its valid byte window. At the start of this stage, a write command is issued to a specified
DDR2 or DDR3 SDRAM address location with a predefined data pattern. This write
command is followed by back-to-back read commands to continuously read data back from
the same address location that was written to.
The algorithm first increments the IDELAY taps for all DQ bits in a byte simultaneously until
an edge is detected. At the end of the IDELAY increments, DQS is at or before the left edge
of the window.
The calibration logic reads data out of the IN_FIFO and records it for comparison. The data
pattern sequence is important for this stage of calibration. No assumption is made about
the initial relationship between DQS and the data window at tap 0 of the fine delay line. The
algorithm then delays DQS using the PHASER_IN fine delay line until a DQ window edge is
detected.
An averaging algorithm is used for data window detection where data is read back over
multiple cycles at the same tap value. The number of sampling cycles is set to 214. In
addition to averaging, there is also a counter to track whether DQS is positioned in the
unstable jitter region. A counter value of 3 means that the sampled data value was constant
for three consecutive tap increments and DQS is considered to be in a stable region. The
counter value is reset to 0 whenever a value different from the previous value is detected.
The next step is to increment the fine phase shift delay line of the DQS PHASER_IN block
one tap at a time until a data mismatch is detected. The data read out of IN_FIFO after the
required settling time is then compared with the recorded data at the previous tap value.
This is repeated until a data mismatch is found, indicating the detection of a valid data
window edge. A valid window is the number of PHASER_IN fine phase shift taps for which
the stable counter value is a constant 3. This algorithm mitigates the risk of detecting a
FALSE valid edge in the unstable jitter regions.
There are three possible scenarios for the initial DQS position with respect to the data
window. The first valid rising edge of DQS could either be in the previous data window, in
the left noise region of the current data window, or just past the left noise region inside the
current data window. The PHASER_IN fine delay line has 64 taps (A bit time worth of taps.
Tap resolution therefore changes with frequency.).
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English