Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 320
UG586 November 30, 2016
www.xilinx.com
Chapter 2: QDR II+ Memory Interface Solution
app_rd_cmd1 Input
Read Command. This signal is used to issue a
read request and indicates that the address on
port 1 is valid.
app_rd_data1[DATA_WIDTH × 2 – 1:0] Output
Read Data. This bus carries the data read back
from the read command issued on
app_rd_cmd1.
app_rd_valid1 Output
Read Valid. This signal indicates that data read
back from memory is now available on
app_rd_data1 and should be sampled.
app_wr_addr0[ADDR_WIDTH – 1:0] Input
Write Address. This bus provides the address
for a write request. It is valid when
app_wr_cmd0 is asserted.
app_wr_bw_n0[BW_WIDTH × BURST_LEN – 1:0] Input
Write Byte Writes. This bus provides the byte
writes to use for a write request. It is valid when
app_wr_cmd0 is asserted. These enables are
active-Low.
app_wr_cmd0 Input
Write Command. This signal is used to issue a
write request and indicates that the
corresponding sideband signals on write port 0
are valid.
app_wr_data0[DATA_WIDTH × BURST_LEN – 1:0] Input
Write Data. This bus provides the data to use
for a write request. It is valid when
app_wr_cmd0 is asserted.
app_wr_addr1[ADDR_WIDTH – 1:0] Input
Write Address. This bus provides the address
for a write request. It is valid when
app_wr_cmd1 is asserted.
app_wr_bw_n1[BW_WIDTH × 2 – 1:0] Input
Write Byte Writes. This bus provides the byte
writes to use for a write request. It is valid when
app_wr_cmd1 is asserted. These enables are
active-Low.
app_wr_cmd1 Input
Write Command. This signal is used to issue a
write request and indicates that the
corresponding sideband signals on write port 1
are valid.
app_wr_data1[DATA_WIDTH × 2 – 1:0] Input
Write Data. This bus provides the data to use
for a write request. It is valid when
app_wr_cmd1 is asserted.
Table 2-7: Client Interface Request Signals (Cont’d)
Signal Direction Description
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Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V

Summary

Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution

Introduction

Overview of the DDR3 and DDR2 SDRAM Memory Interface Solution, its architecture, and features.

Features

Highlights enhancements in 7 series FPGA memory interface solutions over earlier families.

Chapter 2: QDR II+ Memory Interface Solution

Introduction

Details the QDR II+ SRAM Memory Interface Solution, its architecture, and usage.

Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions

Introduction

Explains RLDRAM II/III Memory Interface Solutions, covering architecture, usage, and simulation.

Chapter 4: LPDDR2 SDRAM Memory Interface Solution

Introduction

Introduces the LPDDR2 SDRAM Memory Interface Solution, its core components, and features.

Features

Details enhancements in LPDDR2 SDRAM solutions, including performance and hardware blocks.

Chapter 5: Multicontroller Design

Introduction

Describes specifications, supported features, and pinout rules for multicontroller designs.

Chapter 6: Upgrading the ISE/CORE Generator MIG Core in Vivado

Appendix A: General Memory Routing Guidelines