Xilinx Zynq-7000 - Page 477

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 477
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
DCI (HP banks) or IN_TERM (HR banks) is required at the FPGA to meet the specified
performance. Designs generated by the MIG tool use the DCI standards for Data (DQ) and
Read Clock (QK_P and QK_N) in the High-Performance banks. In the High-Range banks for
RLDRAM II, the MIG tool uses the HSTL_II and DIFF_HSTL_II standards with the internal
termination (IN_TERM) attribute chosen in the GUI.
Table 3-24: RLDRAM II I/O Standards
Signal Direction I/O Standard
rld_ck_p, rld_ck_n Output DIFF_HSTL_I
rld_dk_p, rld_dk_n InOut DIFF_HSTL_II
rld_cs_n Output HSTL_I
rld_we_n Output HSTL_I
rld_ref_n Output HSTL_I
rld_a Output HSTL_I
rld_ba Output HSTL_I
rld_dm Output HSTL_I
rld_dq Input/Output HSTL_II_T_DCI, HSTL_II
rld_qk_p, rld_qk_n Input DIFF_HSTL_II_DCI, DIFF_HSTL_II
Table 3-25: RLDRAM 3 I/O Standards
Signal Direction I/O Standard
rld_ck_p, rld_ck_n Output DIFF_SSTL12
rld_dk_p, rld_dk_n InOut DIFF_SSTL12
rld_cs_n Output SSTL12
rld_we_n Output SSTL12
rld_ref_n Output SSTL12
rld_a Output SSTL12
rld_ba Output SSTL12
rld_dm Output SSTL12
rld_dq Input/Output SSTL12_T_DCI, SSTL12
rld_qk_p, rld_qk_n Input DIFF_SSTL12_DCI, DIFF_SSTL12
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