Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
SEQUENCER
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SEQUENCER FEATURES
The features of the ADuCM356 sequencer are as follows:
► Programmable for cycle accurate applications.
► Four separate command sequences.
► 6 kB SRAM to store sequences.
► FIFO to store measurement results.
► Control via the wake-up timer or direct register write.
► Various interrupts from user maskable sources.
SEQUENCER OVERVIEW
The role of the sequencer is to allow offloading of the low level AFE
operations from the digital die and to provide cyclic accurate control
over the analog DSP blocks. The sequencer handles timing critical
operations without being subject to system load.
Four command sequences are supported by hardware on the
ADuCM356. These sequences can be stored in the SRAM to switch
between different measurement procedures. Only one sequence
can be executed by the sequencer at a time. However, the user can
configure which sequences the sequencer executes and the order
in which they are executed.
The sequencer reads commands from the sequence that is stored
in the command memory and, depending on the command, either
waits a certain amount of time or writes a value to an MMR. The
execution is sequential with no branching. The sequencer cannot
read MMR values or signals from the analog or DSP blocks.
To enable the sequencer, set the SEQEN bit in the SEQCON
register. To disable the sequencer, write 0 to this bit.
The rate at which the sequencer commands are executed is pro-
vided in the SEQWRTMR bits in the SEQCON register. When
a write command is executed by the sequencer, the sequencer
performs the MMR write and then waits SEQWRTMR clock cycles
before fetching the next command in the sequence. The effect is
the same as a write command followed by a wait command. The
main purpose of this setup is to reduce code size when generating
arbitrary waveforms. The SEQWRTMR bits do not have any effect
following a wait or timeout command.
In addition to a single write command being followed by a wait
command, multiple write commands can be executed in succession
followed by a wait command. Any configuration can be rapidly set
up by the sequencer, regardless of the number of register writes
followed by a precisely executed delay.
The sequencer can also be paused by setting the SEQHALT bit
in the SEQCON register. This option applies to each function, in-
cluding FIFO operations, internal timers, and waveform generation.
Reads from the MMRs are allowed when the sequencer is paused.
This mode is intended for debugging during software development.
The number of commands executed by the sequencer can be read
from the SEQCNT register. Each time a command is read from
command memory and executed, the counter increments by 1. To
reset the counter, perform a write to the SEQCNT register.
The sequencer calculates the cyclic redundancy check (CRC) of
all commands it executes. The algorithm used is the CRC-8, using
the x
8
+ x
2
+ x + 1 polynomial. The CRC-8 algorithm performs
on 32-bit input data (sequencer instructions). Each 32‑bit input is
processed in one clock cycle and the result is available immediately
for reading by the host controller. The CRC value can be read
from the SEQCRC register. To reset this register by the same
mechanism as the command count, write to the SEQCNT register.
The SEQCRC register resets to a seed value of 0x01. SEQCRC is
a read only register.
SEQUENCER COMMANDS
Two types of commands can be executed by the sequencer: write
commands and timer commands, which include wait commands
and timeout commands.
Write Command
Use a write instruction to write data to a register. The register
address must lie between 0x400C0000 and 0x400C21FC. Figure
28 shows the format of the instruction. The MSB is equal to 1,
which indicates a write command.
In Figure 28, ADDR is the write address and data is the write data
to be written to the MMR. All write instructions finish within one
cycle.
The address field is seven bits wide to allow access to registers
from Address 0x0 to Address 0x1FC in the AFE register block.
All MMR accesses are 32 bits. Byte and half word accesses are
forbidden. All accesses are write only. There is a direct mapping
between the address field and the MMR address. In Figure 28,
ADDR corresponds to Bits[8:2] of the 16-bit MMR address.
For example, when writing to the WGCON register directly through
the die to die interface, Address 0x400C2014 is used. To write to
the same register using the sequencer, the address field must be
0b0000101 (Bits[8:2] of the address used by the external control-
ler).
The data field is 24 bits wide and only allows writing to the MMR
bits, Bits[23:0]. It is not possible to write to the full 32 bits of the
MMRs via the sequencer. However, Bits[31:24] are not used by any
of the MMRs. Therefore, all assigned MMR bits can be written by
the sequencer.
Timer Command
There are two timer commands in the sequencer, each with a
separate hardware counter.
The wait command introduces wait states in the sequencer exe-
cution. When the programmed counter reaches 0, the execution
resumes by reading the next command from command memory.

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English

Summary

PREFACE

SCOPE

Provides a detailed description of the functionality and features of the ADuCM356.

CLOCKING ARCHITECTURE

DIGITAL DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the digital die system clock.

ANALOG DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the analog die system clock.

POWER MANAGEMENT UNIT

Active Mode

Describes the fully active operating mode where the Arm Cortex-M3 executes from flash and SRAM.

Flexi Mode

Describes the mode where the Arm Cortex-M3 is disabled, allowing peripherals to operate.

Hibernate Mode

Describes the low-power mode where the digital core and most analog blocks are powered down.

SYSTEM RESETS

DIGITAL DIE RESET OPERATION

Explains the reset sources and operation for the digital die, including software resets.

PROGRAMMING, PROTECTION, AND DEBUG

Debug Features

Details the SWD port, flash patch breakpoints, and data watchpoint/trigger units for debugging.

SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS

CORTEX-M3 AND FAULT MANAGEMENT

Describes the system exceptions and fault handling features integrated with the Cortex-M3 processor.

ANALOG DIE CIRCUITRY SUMMARY

ADC, HIGH-SPEED DAC, AND ASSOCIATED AMPLIFIERS OPERATING MODE CONFIGURATION

Configures the operating modes for ADC, High-Speed DAC, and associated amplifiers.

ADC CIRCUIT

ADC CIRCUIT FEATURES

Lists the key features of the ADuCM356's fast multichannel, 16-bit ADC.

LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS

LOW-POWER POTENTIOSTAT AMPLIFIERS

Details the two low-power potentiostat amplifiers for setting external sensor bias voltage.

HIGH-SPEED DAC CIRCUITS

HIGH-SPEED DAC OUTPUT SIGNAL GENERATION

Explains how to generate high-speed DAC output voltage via direct write or waveform generator.

PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH-SPEED DAC AND HIGH-SPEED TIA

DX SWITCHES

Selects pins for the high-speed DAC excitation amplifier output, used for impedance measurements.

SEQUENCER

SEQUENCER COMMANDS

Describes the two types of commands: write commands and timer commands (wait, timeout).

SLEEP AND WAKE-UP TIMER

CONFIGURING A DEFINED SEQUENCE ORDER

Defines the order of sequence execution periodically using the SEQORDER register.

USE CASE CONFIGURATIONS

HIBERNATE MODE WHILE MAINTAINING A DC BIAS TO THE SENSOR

Details setup for hibernate mode while maintaining sensor bias voltage.

DMA CONTROLLER

DMA FEATURES

Lists the features of the ADuCM356's dedicated and independent DMA channels.

FLASH CONTROLLER

SUPPORTED COMMANDS

Summarizes the commands supported by the flash controller for read, write, erase, and signature operations.

REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)

COMMAND REGISTER

Allows execution of specified flash commands like write, erase, abort, and signature generation.

DIGITAL INPUTS AND OUTPUTS

DIGITAL INPUTS AND OUTPUTS OPERATION

Explains how to configure, read, and write digital input and output pins.

I2C SERIAL INTERFACE

I2C OPERATION

Details the steps required to run the I2C peripheral, including startup and modes.

SERIAL PERIPHERAL INTERFACES

SPI OPERATION

Describes the operation of the SPI interface, including initiator and target modes.

REGISTER SUMMARY: SPI0/SPI1

STATUS REGISTERS

Provides status information for SPI0 and SPI1, including ready, overflow, and error conditions.

REGISTER DETAILS: UART

INTERRUPT ENABLE REGISTER

Configures which interrupt sources generate an interrupt for the UART.

DIGITAL DIE GENERAL-PURPOSE TIMERS

GENERAL-PURPOSE TIMER OPERATIONS

Explains the operation of timers in free running mode and periodic mode.

REGISTER SUMMARY: ANALOG DIE GENERAL-PURPOSE TIMERS

CONTROL REGISTER

Controls timer operation, including clock source, mode, and event selection.

REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER

STATUS 0 REGISTER

Provides status information for WUT operation, including synchronization and pending writes.

CYCLIC REDUNDANCY CHECK

CRC OPERATING MODES

Details the core access and DMA access modes for CRC calculation.

REGISTER SUMMARY: CRC

CRC CONTROL REGISTER

Controls the CRC peripheral, including enabling, mirroring, and calculation order.

HARDWARE DESIGN CONSIDERATIONS

SERIAL WIRE DEBUG INTERFACE

Describes the SWD interface for debugging and programming, replacing JTAG.