Reference Manual ADuCM356
REGISTER DETAILS: DMA
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Table 215. Bit Descriptions for SRCADDR_SET (Continued)
Bits Bit Name Settings Description Reset Access
0 When read as 0, Channel C source address decrement is disabled. When written as 0, no effect.
Use the SRCADDR_CLR register to disable source address decrement on Channel C.
1 When read as 1, Channel C source address decrement is enabled. When written as 1, source
address decrement on Channel C is enabled.
CHANNEL SOURCE ADDRESS DECREMENT ENABLE CLEAR REGISTER
Address: 0x40010814, Reset: 0x00000000, Name: SRCADDR_CLR
Table 216. Bit Descriptions for SRCADDR_CLR
Bits Bit Name Settings Description Reset Access
[31:24] Reserved Reserved. 0x00 R
[23:0] CHAN Disable Source Address Decrement. This register enables the user to configure a DMA channel
to use the default source address in increment mode. Each bit of the register represents the
corresponding channel number in the DMA controller. Bit 0 corresponds to DMA Channel 0. Bit M −
1 corresponds to DMA Channel M – 1.
0x000000 W
0 No effect. Use the SRCADDR_SET register to enable source address decrement on Channel C.
1 Disables address source decrement on Channel C.
CHANNEL DESTINATION ADDRESS DECREMENT ENABLE SET REGISTER
Address: 0x40010818, Reset: 0x00000000, Name: DSTADDR_SET
Table 217. Bit Descriptions for DSTADDR_SET
Bits Bit Name Settings Description Reset Access
[31:24] Reserved Reserved. 0x00 R
[23:0] CHAN Destination Address Decrement Status and Configure Destination Address Decrement. The
DSTADDR_SET register is used to configure the destination address of a DMA channel to
decrement the address instead of incrementing the address after each access. Each bit of the
register represents the corresponding channel number in the DMA controller. Bit 0 corresponds to
DMA Channel 0. Bit M − 1 corresponds to DMA Channel M – 1.
0x000000 R/W
0 When read as 0, Channel C destination address decrement is disabled. When written as 0, no
effect. Use the DSTADDR_CLR register to disable destination address decrement on Channel C.
1 When read as 1, Channel C destination address decrement is enabled. When written as 1,
destination address decrement on Channel C is enabled.
CHANNEL DESTINATION ADDRESS DECREMENT ENABLE CLEAR REGISTER
Address: 0x4001081C, Reset: 0x00000000, Name: DSTADDR_CLR
Table 218. Bit Descriptions for DSTADDR_CLR
Bits Bit Name Settings Description Reset Access
[31:24] Reserved Reserved. 0x00 R
[23:0] CHAN Disable Destination Address Decrement. This register enables the user to configure a DMA
channel to use the default destination address in increment mode. Each bit of the register
represents the corresponding channel number in the DMA controller. Bit 0 corresponds to DMA
Channel 0. Bit M − 1 corresponds to DMA Channel M – 1.
0x000000 W
0 No effect. Use the DSTADDR_SET register to enable destination address decrement on Channel
C.
1 Disables destination address decrement on Channel C.
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