Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
AFE INTERRUPTS
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There are interrupt options available on the ADuCM356 analog
front end that can be configured to toggle the internal GPIO pin
on the digital die. The GPIO pin is connected internally and is not
bonded out of the LGA package.
INTERRUPT CONTROLLER INTERRUPTS
The interrupt controller is divided into two blocks. Each block
consists of an INTCSELx register and an INTCFLAGx register.
Only INTCSEL0 interrupts are connected to the digital die by the
internal GPIO pin. The INTCSEL1 interrupts are only used for
polling. The INTCPOL and INTCCLR registers are common to both
blocks. When an interrupt is enabled in the INTCSELx register, the
corresponding bit in the INTCFLAGx register is set. The available
interrupt sources are shown in Table 173.
CONFIGURING THE INTERRUPTS
The first step to configure the INTC interrupts is to configure the
digital die GPIO pin that connects internally to the AFE interrupt
controller output. To configure the GPIO pin, take the following
steps:
1. Configure the internal GPIO2 Pin 1 as a GPIO as follows:
DioCfgPin(pADI_GPIO2, PIN1, 0);
2. Configure the internal P2.1 pin as an input as follows:
DioIenPin(pADI_GPIO2, PIN1, 1); /* Enable
P2.1 input path. */
3. Enable External Interrupt 3 and configure for falling edge as
follows:
EiCfg(EXTINT3, INT_EN, INT_FALL); /* Fall►
ing edge. */
4. Enable the interrupt in the NVIC as follows:
NVIC_EnableIRQ(AFE_EVT3_IRQn);
When these steps are complete, the digital die is configured for
INTC interrupts. To configure the AFE INTC interrupts, first write
to the INCT0POL to configure the polarity. To enable the required
interrupt, write to the INTCSEL0 register. To clear an interrupt
source, write to the corresponding bit in the INTCCLR register.
CUSTOM INTERRUPTS
Four custom interrupt sources are selectable by the user in the
INTCSELx register, Bits[12:9]. For these custom interrupts to gen-
erate an interrupt event, write to the corresponding bit in the
AFEGENINTSTA register. It is only possible to write to this register
via the sequencer.
Table 173. Interrupt Sources Summary
INTCFLAGx Register Flag Name Interrupt Source Description
FLAG0 ADC result IRQ status.
FLAG1 DFT result IRQ status.
FLAG2 Sinc2 filter result ready IRQ status.
FLAG3 Temperature result IRQ status.
FLAG4 ADC minimum fail IRQ status.
FLAG5 ADC maximum fail IRQ status.
FLAG6 ADC delta fail IRQ status.
FLAG7 Mean IRQ status.
FLAG13 Bootload done IRQ status.
FLAG15 End of sequence IRQ status.
FLAG16 Sequencer timeout finished IRQ status (see the Timer Command section).
FLAG17 Sequencer timeout command error IRQ status (see the Timer Command section).
FLAG23 Data FIFO full IRQ status.
FLAG24 Data FIFO empty IRQ status.
FLAG25 Data FIFO threshold IRQ status, threshold value set in DATAFIFOTHRES register.
FLAG26 Data FIFO overflow IRQ status.
FLAG27 Data FIFO underflow IRQ status.
FLAG29 Outlier IRQ status, detects when an outlier is detected.
FLAG31 Attempt to break IRQ status. This interrupt is set if a Sequence B request occurs when Sequence A is running. This interrupt
indicates that Sequence B is ignored.

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English

Summary

PREFACE

SCOPE

Provides a detailed description of the functionality and features of the ADuCM356.

CLOCKING ARCHITECTURE

DIGITAL DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the digital die system clock.

ANALOG DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the analog die system clock.

POWER MANAGEMENT UNIT

Active Mode

Describes the fully active operating mode where the Arm Cortex-M3 executes from flash and SRAM.

Flexi Mode

Describes the mode where the Arm Cortex-M3 is disabled, allowing peripherals to operate.

Hibernate Mode

Describes the low-power mode where the digital core and most analog blocks are powered down.

SYSTEM RESETS

DIGITAL DIE RESET OPERATION

Explains the reset sources and operation for the digital die, including software resets.

PROGRAMMING, PROTECTION, AND DEBUG

Debug Features

Details the SWD port, flash patch breakpoints, and data watchpoint/trigger units for debugging.

SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS

CORTEX-M3 AND FAULT MANAGEMENT

Describes the system exceptions and fault handling features integrated with the Cortex-M3 processor.

ANALOG DIE CIRCUITRY SUMMARY

ADC, HIGH-SPEED DAC, AND ASSOCIATED AMPLIFIERS OPERATING MODE CONFIGURATION

Configures the operating modes for ADC, High-Speed DAC, and associated amplifiers.

ADC CIRCUIT

ADC CIRCUIT FEATURES

Lists the key features of the ADuCM356's fast multichannel, 16-bit ADC.

LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS

LOW-POWER POTENTIOSTAT AMPLIFIERS

Details the two low-power potentiostat amplifiers for setting external sensor bias voltage.

HIGH-SPEED DAC CIRCUITS

HIGH-SPEED DAC OUTPUT SIGNAL GENERATION

Explains how to generate high-speed DAC output voltage via direct write or waveform generator.

PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH-SPEED DAC AND HIGH-SPEED TIA

DX SWITCHES

Selects pins for the high-speed DAC excitation amplifier output, used for impedance measurements.

SEQUENCER

SEQUENCER COMMANDS

Describes the two types of commands: write commands and timer commands (wait, timeout).

SLEEP AND WAKE-UP TIMER

CONFIGURING A DEFINED SEQUENCE ORDER

Defines the order of sequence execution periodically using the SEQORDER register.

USE CASE CONFIGURATIONS

HIBERNATE MODE WHILE MAINTAINING A DC BIAS TO THE SENSOR

Details setup for hibernate mode while maintaining sensor bias voltage.

DMA CONTROLLER

DMA FEATURES

Lists the features of the ADuCM356's dedicated and independent DMA channels.

FLASH CONTROLLER

SUPPORTED COMMANDS

Summarizes the commands supported by the flash controller for read, write, erase, and signature operations.

REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)

COMMAND REGISTER

Allows execution of specified flash commands like write, erase, abort, and signature generation.

DIGITAL INPUTS AND OUTPUTS

DIGITAL INPUTS AND OUTPUTS OPERATION

Explains how to configure, read, and write digital input and output pins.

I2C SERIAL INTERFACE

I2C OPERATION

Details the steps required to run the I2C peripheral, including startup and modes.

SERIAL PERIPHERAL INTERFACES

SPI OPERATION

Describes the operation of the SPI interface, including initiator and target modes.

REGISTER SUMMARY: SPI0/SPI1

STATUS REGISTERS

Provides status information for SPI0 and SPI1, including ready, overflow, and error conditions.

REGISTER DETAILS: UART

INTERRUPT ENABLE REGISTER

Configures which interrupt sources generate an interrupt for the UART.

DIGITAL DIE GENERAL-PURPOSE TIMERS

GENERAL-PURPOSE TIMER OPERATIONS

Explains the operation of timers in free running mode and periodic mode.

REGISTER SUMMARY: ANALOG DIE GENERAL-PURPOSE TIMERS

CONTROL REGISTER

Controls timer operation, including clock source, mode, and event selection.

REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER

STATUS 0 REGISTER

Provides status information for WUT operation, including synchronization and pending writes.

CYCLIC REDUNDANCY CHECK

CRC OPERATING MODES

Details the core access and DMA access modes for CRC calculation.

REGISTER SUMMARY: CRC

CRC CONTROL REGISTER

Controls the CRC peripheral, including enabling, mirroring, and calculation order.

HARDWARE DESIGN CONSIDERATIONS

SERIAL WIRE DEBUG INTERFACE

Describes the SWD interface for debugging and programming, replacing JTAG.