Reference Manual ADuCM356
REGISTER DETAILS: GENERAL-PURPOSE TIMERS
analog.com Rev. A | 269 of 312
Table 345. Bit Descriptions for GPT0_CTL, GPT1_CTL, GPT2_CTL (Continued)
Bits Bit Name Settings Description Reset Access
4 EN Timer Enable. Used to enable and to disable the timer. Clearing this bit resets the timer, including the
GPTx_CURCNT register.
0x0 R/W
0 Timer is disabled. Default.
1 Timer is enabled.
3 MODE Timer Mode. This bit controls whether the timer runs in periodic or free running mode. In periodic mode,
the up or down counter starts at the defined load value (GPTx_LOAD). In free running mode, the up or
down counter starts at 0x0000 or 0xFFFF depending on whether the timer is counting up or down.
0x1 R/W
0 Timer runs in free running mode.
1 Timer runs in periodic mode. Default.
2 UP Count Up. Used to control whether the timer increments (counts up) or decrements (counts down) the up
or down counter.
0x0 R/W
0 Timer is set to count down. Default.
1 Timer is set to count up.
[1:0] PRE Prescaler. Controls the prescaler division factor, applied to the selected clock of the timer. If Clock Source
0 (PCLK) or Clock Source 1 (HCLK) is selected, a prescaler value of 0 means divide by 4. Otherwise, it
means divide by 1.
0x2 R/W
00 Source clock/1 or source clock/4. Divide by 1 if SYNCBYP = 1, or divide by 4 if SYNCBYP = 0.
01 Source clock/16.
10 Source clock/64.
11 Source clock/256.
CLEAR INTERRUPT REGISTERS
Address: 0x4000000C, Reset: 0x0000, Name: GPT0_CLRINT
Address: 0x4000040C, Reset: 0x0000, Name: GPT1_CLRINT
Address: 0x4000080C, Reset: 0x0000, Name: GPT2_CLRINT
Table 346. Bit Descriptions for GPT0_CLRINT, GPT1_CLRINT, GPT2_CLRINT
Bits Bit Name Settings Description Reset Access
[15:2] Reserved Reserved. 0x000 R
1 EVTCAPT Clear Captured Event Interrupt. This bit is used to clear a capture event interrupt. 0x0 W1C
0 No effect.
1 Clear the capture event interrupt.
0 TIMEOUT Clear Timeout Interrupt. This bit is used to clear a timeout interrupt. 0x0 W1C
0 No effect.
1 Clears the timeout interrupt.
CAPTURE REGISTERS
Address: 0x40000010, Reset: 0x0000, Name: GPT0_CAPTURE
Address: 0x40000410, Reset: 0x0000, Name: GPT1_CAPTURE
Address: 0x40000810, Reset: 0x0000, Name: GPT2_CAPTURE
Table 347. Bit Descriptions for GPT0_CAPTURE, GPT1_CAPTURE, GPT2_CAPTURE
Bits Bit Name Settings Description Reset Access
[15:0] VALUE 16-Bit Captured Value. GPTx_CAPTURE holds its value until GPTx_CLRINT, Bit 1 is set by user code.
GPTx_CAPTURE is not overwritten even if another event occurs without writing to GPTx_CLRINT, Bit 1.
0x0000 R