Reference Manual ADuCM356
TABLE OF CONTENTS
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Preface.................................................................. 1
Scope.................................................................... 1
Using the ADuCM356 Hardware Reference
Manual.................................................................9
Number Notations.............................................. 9
Register Access Conventions............................ 9
ADuCM356 Overview.......................................... 10
Main Features of the ADuCM356.....................10
Clocking Architecture...........................................12
Clocking Architecture Operation.......................12
Required Clock Ratio Between Digital Die
and Analog Die System Clocks...................... 12
Digital Die Clock Features................................12
Analog Die Clock Features...............................12
Clock Gating.....................................................13
Connecting AFE Die Clock to Digital Die
Clock Input..................................................... 13
Register Summary: Clock Architecture................15
Register Details: Clock Architecture.................... 16
Key Protection for CTL Register.......................16
Oscillator Control Register............................... 16
Clock Control 0 Register.................................. 16
Clock Dividers Register....................................17
User Clock Gating Control Register................. 17
Clocking Status Register..................................18
Clock Divider Configuration Register............... 18
Clock Gate Enable Register.............................19
Clock Select Register.......................................19
GPIO Clock Mux Select to GPIO1 Pin
Register..........................................................20
Key Protection for CLKCON0 Register............ 20
Clock Control of Low-Power TIA Chop,
Watchdog, and Wake-Up Timers Register..... 20
Key Protection for OSCCON Register..............21
Oscillator Control Register............................... 21
High-Power Oscillator Configuration Register..22
Power Mode Configuration Register................ 22
Power Management Unit..................................... 23
Power Management Unit Features...................23
Power Management Unit Operation.................23
Code Examples................................................24
Monitor Voltage Control....................................25
Register Summary: Power Management Unit..... 27
Register Details: Power Management Unit..........28
Power Supply Monitor Interrupt Enable
Register..........................................................28
Power Supply Monitor Status Register.............28
Power Mode Register.......................................29
Key Protection for PWRMOD and
SRAMRET Register....................................... 29
Control for Retention SRAM During
Hibernate Mode Register............................... 29
High-Power Buck Control Register...................30
Control for SRAM Parity and Instruction
SRAM Register...............................................30
Initialization Status Register.............................31
Power Modes Register.....................................32
Key Protection for PWRMOD Register ............32
Arm Cortex-M3 Processor................................... 33
Arm Cortex-M3 Processor Features.................33
Arm Cortex-M3 Processor Operation...............33
Arm Cortex-M3 Processor Related
Documents..................................................... 34
System Resets.................................................... 35
Digital Die Reset Operation..............................35
Register Summary: System Resets.....................36
Register Details: System Resets......................... 37
Digital Die Reset Status Register.....................37
Always On Reset Status Register.................... 37
Analog Die Status Register.............................. 37
Programming, Protection, and Debug................. 38
Booting............................................................. 38
Security Features............................................. 38
Safety Features................................................38
System Exceptions and Peripheral Interrupts..... 39
Cortex-M3 and Fault Management...................39
Interrupt Sources from the Analog Die.............41
Clearing Analog Die Interrupt Sources.............42
Cortex-M3 NVIC Register List..........................42
External Interrupt Configuration....................... 43
Register Summary: System Exceptions and
Peripheral Interrupts.......................................... 44
Register Details: System Exceptions and
Peripheral Interrupts.......................................... 45
External Interrupt Configuration 0 Register......45
External Wake-Up Interrupt Status Register.... 46
External Interrupt Clear Register......................46
Nonmaskable Interrupt Clear Register.............46
Analog Die Interrupt Enable Register...............46
Analog Die Circuitry Summary............................ 48
ADC, High-Speed DAC, and Associated
Amplifiers Operating Mode Configuration ..... 48
System Bandwidth Configuration..................... 48
Register Summary: Analog Die Circuitry............. 50
Register Details: Analog Die Circuitry................. 51
AFE Configuration Register..............................51
ADC Circuit..........................................................53
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