Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
DIGITAL INPUTS AND OUTPUTS
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The following is example code for the GPIO pin interrupt handler
routine:
void GPIO_A_Int_Handler()
{
unsigned int uiIntSta = 0;
uiIntSta = pADI_GPIO1->INT;
if ((uiIntSta & 0x2) ==0x2) // interrupt
expected on P1.1
{
pADI_GPIO1->INT |= 0x2;
}
}
The following is example code to set P0.3/SPI0_CS as an output.
Write to GP0OUT, GP0SET, GP0CLR, and GP0TGL to set the level
on P0.3/SPI0_CS:
pADI_GPIO0->OEN |= 0x8; //
Configure P0.3 as an output
DIGITAL DIE PORT MUX
This block provides control over the GPIO functionality of specified
pins. Some pins have the ability to work as a GPIO or perform other
specific functions. Only configuration of the P2.4 pin of Port 2 is
permitted. Attempted writes to other port pins are not allowed. Any
blank cells in Table 255 are not applicable.
Table 255. GPIO Multiplex Table
GPIO Pin
Configuration Modes
00 01 10 11
GP0 (GP0CON Controls These Bits)
P0.0/SPI0_CLK GPIO (GP0CON, Bits[1:0] = 0x0) SPI0 serial clock (SCLK) (GP0CON, Bits[1:0] = 0x1)
P0.1/SPI0_MOSI GPIO (GP0CON, Bits[3:2] = 0x0) SPI0 MOSI (GP0CON, Bits[3:2] = 0x1)
P0.2/SPI0_MISO GPIO (GP0CON, Bits[5:4] = 0x0) SPI0 MISO (GP0CON, Bits[5:4] = 0x1)
P0.3/SPI0_CS GPIO (GP0CON, Bits[7:6] = 0x0) SPI0 chip select (GP0CON, Bits[7:6] = 0x1) SPI1 ready (GP0CON,
Bits[7:6] = 0x3)
P0.4/I2C_SCL GPIO (GP0CON, Bits[9:8] = 0x0) I2C I2C_SCL (GP0CON, Bits[9:8] = 0x1)
P0.5/I2C_SDA GPIO (GP0CON, Bits[11:10] = 0x0) I2C I2C_SDA (GP0CON, Bits[11:10] = 0x1)
P0.10/UART_SOUT GPIO (GP0CON, Bits[21:20] = 0x0) UART SOUT pin (GP0CON, Bits[21:20] = 0x1)
P0.11/UART_SIN GPIO (GP0CON, Bits[23:22] = 0x0) UART SIN pin (GP0CON, Bits[23:22] = 0x1)
GP1 (GP1CON Controls These Bits)
P1.0/SYS_WAKE GPIO (GP1CON, Bits[1:0] = 0x0)
BM/P1.1 GPIO boot (GP1CON, Bits[3:2] =
0x0)
GPIO (GP1CON, Bits[3:2] = 0x1)
P1.2/SPI1_CLK GPIO (GP1CON, Bits[5:4] = 0x0) SPI1 SCLK (GP1CON, Bits[5:4] = 0x1)
P1.3/SPI1_MOSI GPIO (GP1CON, Bits[7:6] = 0x0) SPI1 MOSI (GP1CON, Bits[7:6] = 0x1)
P1.4/SPI1_MISO GPIO (GP1CON, Bits[9:8] = 0x0) SPI1 MISO (GP1CON, Bits[9:8] = 0x1)
P1.5/SPI1_CS GPIO (GP1CON, Bits[11:10] = 0x0) SPI1 chip select (GP1CON, Bits[11:10] = 0x1)
P2.4 GPIO (GP2CON, Bits[9:8] = 0x0)
AFE DIE DIGITAL PORT MUX
This block provides control over the three digital die GPIO pins.
Two of these pins are bonded out as GPIO0/PWM0 and GPIO1/
PWM1. The third pin, referred to as P2.2, is an internal pin bonded
to the digital die P0.10/UART_SOUT pin and supports connecting
the AFE die system clock to the digital die.
Table 256. AFE Die GPIO Mux Table
GPIO
Configuration Modes (GP2CON Controls These Bits)
00 01 10 11
GPIO0 Reserved PWM0 (GP2CON, Bits[1:0] = 0x1) GPIO (GP2CON, Bits[1:0] = 0x2) Reserved
GPIO1 Reserved PWM1 (GP2CON, Bits[3:2] = 0x1) GPIO (GP2CON, Bits[3:2] = 0x2) Reserved
P2.2 (Internal Only) CLK_OUT (GP2CON, Bits[5:4] = 0x0) Reserved Reserved Reserved

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English

Summary

PREFACE

SCOPE

Provides a detailed description of the functionality and features of the ADuCM356.

CLOCKING ARCHITECTURE

DIGITAL DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the digital die system clock.

ANALOG DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the analog die system clock.

POWER MANAGEMENT UNIT

Active Mode

Describes the fully active operating mode where the Arm Cortex-M3 executes from flash and SRAM.

Flexi Mode

Describes the mode where the Arm Cortex-M3 is disabled, allowing peripherals to operate.

Hibernate Mode

Describes the low-power mode where the digital core and most analog blocks are powered down.

SYSTEM RESETS

DIGITAL DIE RESET OPERATION

Explains the reset sources and operation for the digital die, including software resets.

PROGRAMMING, PROTECTION, AND DEBUG

Debug Features

Details the SWD port, flash patch breakpoints, and data watchpoint/trigger units for debugging.

SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS

CORTEX-M3 AND FAULT MANAGEMENT

Describes the system exceptions and fault handling features integrated with the Cortex-M3 processor.

ANALOG DIE CIRCUITRY SUMMARY

ADC, HIGH-SPEED DAC, AND ASSOCIATED AMPLIFIERS OPERATING MODE CONFIGURATION

Configures the operating modes for ADC, High-Speed DAC, and associated amplifiers.

ADC CIRCUIT

ADC CIRCUIT FEATURES

Lists the key features of the ADuCM356's fast multichannel, 16-bit ADC.

LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS

LOW-POWER POTENTIOSTAT AMPLIFIERS

Details the two low-power potentiostat amplifiers for setting external sensor bias voltage.

HIGH-SPEED DAC CIRCUITS

HIGH-SPEED DAC OUTPUT SIGNAL GENERATION

Explains how to generate high-speed DAC output voltage via direct write or waveform generator.

PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH-SPEED DAC AND HIGH-SPEED TIA

DX SWITCHES

Selects pins for the high-speed DAC excitation amplifier output, used for impedance measurements.

SEQUENCER

SEQUENCER COMMANDS

Describes the two types of commands: write commands and timer commands (wait, timeout).

SLEEP AND WAKE-UP TIMER

CONFIGURING A DEFINED SEQUENCE ORDER

Defines the order of sequence execution periodically using the SEQORDER register.

USE CASE CONFIGURATIONS

HIBERNATE MODE WHILE MAINTAINING A DC BIAS TO THE SENSOR

Details setup for hibernate mode while maintaining sensor bias voltage.

DMA CONTROLLER

DMA FEATURES

Lists the features of the ADuCM356's dedicated and independent DMA channels.

FLASH CONTROLLER

SUPPORTED COMMANDS

Summarizes the commands supported by the flash controller for read, write, erase, and signature operations.

REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)

COMMAND REGISTER

Allows execution of specified flash commands like write, erase, abort, and signature generation.

DIGITAL INPUTS AND OUTPUTS

DIGITAL INPUTS AND OUTPUTS OPERATION

Explains how to configure, read, and write digital input and output pins.

I2C SERIAL INTERFACE

I2C OPERATION

Details the steps required to run the I2C peripheral, including startup and modes.

SERIAL PERIPHERAL INTERFACES

SPI OPERATION

Describes the operation of the SPI interface, including initiator and target modes.

REGISTER SUMMARY: SPI0/SPI1

STATUS REGISTERS

Provides status information for SPI0 and SPI1, including ready, overflow, and error conditions.

REGISTER DETAILS: UART

INTERRUPT ENABLE REGISTER

Configures which interrupt sources generate an interrupt for the UART.

DIGITAL DIE GENERAL-PURPOSE TIMERS

GENERAL-PURPOSE TIMER OPERATIONS

Explains the operation of timers in free running mode and periodic mode.

REGISTER SUMMARY: ANALOG DIE GENERAL-PURPOSE TIMERS

CONTROL REGISTER

Controls timer operation, including clock source, mode, and event selection.

REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER

STATUS 0 REGISTER

Provides status information for WUT operation, including synchronization and pending writes.

CYCLIC REDUNDANCY CHECK

CRC OPERATING MODES

Details the core access and DMA access modes for CRC calculation.

REGISTER SUMMARY: CRC

CRC CONTROL REGISTER

Controls the CRC peripheral, including enabling, mirroring, and calculation order.

HARDWARE DESIGN CONSIDERATIONS

SERIAL WIRE DEBUG INTERFACE

Describes the SWD interface for debugging and programming, replacing JTAG.