Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)
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USER CONFIGURATION REGISTER
Address: 0x40018030, Reset: 0x00000000, Name: UCFG
User key is required. Write to this register to enable user control of DMA and autoincrement features. When user code has finished accessing
this register, write arbitrary data to the key register to reassert protection.
Table 236. Bit Descriptions for UCFG
Bits Bit Name Settings Description Reset Access
[31:2] Reserved Reserved. 0x0 R
1 AUTOINCEN Automatic Address Increment for Keyhole Access. When this bit is set, KH_ADDR automatically
increments by 0x8 during each write command or after each read command, enabling user code to
write a series of sequential flash locations without having to manually set the flash address for each
write. The KH_ADDR register is incremented, and can be observed by user code when STAT, Bit 5
is asserted during a write command or after a read command. When this bit is set, user code cannot
directly modify KH_ADDR.
0x0 R/W
0 KHDMAEN Keyhole DMA Enable. The flash controller interacts with the DMA controller when this bit is set.
Prior to setting this bit, write the starting address to the KH_ADDR register. Then configure the DMA
controller to write data to the KH_DATA1 register (address must be data word aligned), to always
write pairs of 32-bit words (R_POWER = 1), and to write an integer number of data pairs (for an
odd number of words, user code must write one word manually without the help of DMA). All DMA
writes automatically increment the target address (similar to the behavior of UCFG, Bit 1). The DMA
controller can only be used to write sequential addresses starting from the value of KH_ADDR. The
flash controller automatically begins write operations each time the DMA controller provides a pair
of words to write. Interaction with the DMA controller is designed to use burst writes, which can
significantly reduce overall programming time.
0x0 R/W
IRQ ABORT ENABLE (LOWER BITS) REGISTER
Address: 0x4001803C, Reset: 0x00000000, Name: ABORT_EN_LO
Table 237. Bit Descriptions for ABORT_EN_LO
Bits Bit Name Settings Description Reset Access
[31:0] VALUE[31:0] System IRQ Abort Enable. To allow a system interrupt to abort an ongoing flash command, write 1 to the
bit in this register corresponding with the desired system IRQ number.
0x0 R/W
IRQ ABORT ENABLE (UPPER BITS) REGISTER
Address: 0x40018040, Reset: 0x00000000, Name: ABORT_EN_HI
Table 238. Bit Descriptions for ABORT_EN_HI
Bits Bit Name Settings Description Reset Access
[31:0] VALUE[63:32] System IRQ Abort Enable. To allow a system interrupt to abort an ongoing flash command, write 1 to
the bit in this register corresponding with the desired system IRQ number.
0x0 R/W
ECC CONFIGURATION REGISTER
Address: 0x40018044, Reset: 0x00000002, Name: ECC_CFG
Table 239. Bit Descriptions for ECC_CFG
Bits Bit Name Settings Description Reset Access
[31:8] PTR ECC Start Page Pointer. Write Bits[31:8] of the start page address into Bits[31:8] of this register. This bit
is a byte address for any page in user flash. The bottom bits of this address are ignored by the flash
controller, forming a page address. When ECC is enabled and user code reads any address from within
the page specified, ECC functions are performed. Reads from less significant pages bypass ECC entirely.
0x0 R/W
[7:2] Reserved Reserved. 0x0 R

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English

Summary

PREFACE

SCOPE

Provides a detailed description of the functionality and features of the ADuCM356.

CLOCKING ARCHITECTURE

DIGITAL DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the digital die system clock.

ANALOG DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the analog die system clock.

POWER MANAGEMENT UNIT

Active Mode

Describes the fully active operating mode where the Arm Cortex-M3 executes from flash and SRAM.

Flexi Mode

Describes the mode where the Arm Cortex-M3 is disabled, allowing peripherals to operate.

Hibernate Mode

Describes the low-power mode where the digital core and most analog blocks are powered down.

SYSTEM RESETS

DIGITAL DIE RESET OPERATION

Explains the reset sources and operation for the digital die, including software resets.

PROGRAMMING, PROTECTION, AND DEBUG

Debug Features

Details the SWD port, flash patch breakpoints, and data watchpoint/trigger units for debugging.

SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS

CORTEX-M3 AND FAULT MANAGEMENT

Describes the system exceptions and fault handling features integrated with the Cortex-M3 processor.

ANALOG DIE CIRCUITRY SUMMARY

ADC, HIGH-SPEED DAC, AND ASSOCIATED AMPLIFIERS OPERATING MODE CONFIGURATION

Configures the operating modes for ADC, High-Speed DAC, and associated amplifiers.

ADC CIRCUIT

ADC CIRCUIT FEATURES

Lists the key features of the ADuCM356's fast multichannel, 16-bit ADC.

LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS

LOW-POWER POTENTIOSTAT AMPLIFIERS

Details the two low-power potentiostat amplifiers for setting external sensor bias voltage.

HIGH-SPEED DAC CIRCUITS

HIGH-SPEED DAC OUTPUT SIGNAL GENERATION

Explains how to generate high-speed DAC output voltage via direct write or waveform generator.

PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH-SPEED DAC AND HIGH-SPEED TIA

DX SWITCHES

Selects pins for the high-speed DAC excitation amplifier output, used for impedance measurements.

SEQUENCER

SEQUENCER COMMANDS

Describes the two types of commands: write commands and timer commands (wait, timeout).

SLEEP AND WAKE-UP TIMER

CONFIGURING A DEFINED SEQUENCE ORDER

Defines the order of sequence execution periodically using the SEQORDER register.

USE CASE CONFIGURATIONS

HIBERNATE MODE WHILE MAINTAINING A DC BIAS TO THE SENSOR

Details setup for hibernate mode while maintaining sensor bias voltage.

DMA CONTROLLER

DMA FEATURES

Lists the features of the ADuCM356's dedicated and independent DMA channels.

FLASH CONTROLLER

SUPPORTED COMMANDS

Summarizes the commands supported by the flash controller for read, write, erase, and signature operations.

REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)

COMMAND REGISTER

Allows execution of specified flash commands like write, erase, abort, and signature generation.

DIGITAL INPUTS AND OUTPUTS

DIGITAL INPUTS AND OUTPUTS OPERATION

Explains how to configure, read, and write digital input and output pins.

I2C SERIAL INTERFACE

I2C OPERATION

Details the steps required to run the I2C peripheral, including startup and modes.

SERIAL PERIPHERAL INTERFACES

SPI OPERATION

Describes the operation of the SPI interface, including initiator and target modes.

REGISTER SUMMARY: SPI0/SPI1

STATUS REGISTERS

Provides status information for SPI0 and SPI1, including ready, overflow, and error conditions.

REGISTER DETAILS: UART

INTERRUPT ENABLE REGISTER

Configures which interrupt sources generate an interrupt for the UART.

DIGITAL DIE GENERAL-PURPOSE TIMERS

GENERAL-PURPOSE TIMER OPERATIONS

Explains the operation of timers in free running mode and periodic mode.

REGISTER SUMMARY: ANALOG DIE GENERAL-PURPOSE TIMERS

CONTROL REGISTER

Controls timer operation, including clock source, mode, and event selection.

REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER

STATUS 0 REGISTER

Provides status information for WUT operation, including synchronization and pending writes.

CYCLIC REDUNDANCY CHECK

CRC OPERATING MODES

Details the core access and DMA access modes for CRC calculation.

REGISTER SUMMARY: CRC

CRC CONTROL REGISTER

Controls the CRC peripheral, including enabling, mirroring, and calculation order.

HARDWARE DESIGN CONSIDERATIONS

SERIAL WIRE DEBUG INTERFACE

Describes the SWD interface for debugging and programming, replacing JTAG.