Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
I
2
C SERIAL INTERFACE
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In initiator mode, the steps are as follows:
1. Clear MCTL, Bit 0 to 0 and disable the I
2
C initiator.
2. Set SHCTL, Bit 0 to 1, which is a write only register. Writing
to this bit resets the start and stop detection circuits of the I
2
C
block and clears MSTAT, Bit 10.
3. Set MCTL, Bit 0 to 1 to reenable the I
2
C initiator.
In target mode, the steps are as follows:
1. Clear SCTL, Bit 0 to 0 and disable the I
2
C target.
2. Set SHCTL, Bit 0 to 1, which is a write only register. Writing
to this bit resets the start and stop detection circuits of the I
2
C
block.
3. Set SCTL, Bit 0 to 1 to reenable the I
2
C target.
I
2
C OPERATING MODES
Initiator Transfer Initiation
If the initiator enable bit (MCTL, Bit 0) is set, an initiator transfer
sequence is initiated by writing a value to the ADR1 register. If there
is valid data in the MTX register, it is the first byte transferred in the
sequence after the address byte during a write sequence.
Target Transfer Initiation
If the target enable bit (SCTL, Bit 0) is set, a target transfer
sequence is monitored for the device address in Register ID0,
Register ID1, Register ID2, or Register ID3. If the device address is
recognized, the device participates in the target transfer sequence.
Note that a target operation always starts with the assertion of one
of three interrupt sources: a read request (MRXREQ, SRXREQ),
a write request (MTXREQ, STXREQ), or a general call interrupt
(GCINT). The software must always look for a stop interrupt to
ensure that the transaction has completed correctly and to deassert
the stop interrupt status bit.
Receive and Transmit Data FIFOs
The transmit data path consists of an initiator and target transmit
FIFO (each two bytes deep), the MTX register and STX register,
and a transmit shifter. The transmit status bits, MSTAT, Bits[1:0],
and SSTAT, Bit 0 denote whether there is valid data in the transmit
FIFO. Data from the transmit FIFO is loaded into the transmit shifter
when a serial byte begins transmission. If the transmit FIFO is
not full during an active transfer sequence, the transmit request
bit (MSTAT, Bit 2 or SSTAT, Bit 2) asserts. Figure 60 shows the
effect of not having the target transmit FIFO full at the start of a
read request from an initiator. An extra transmit interrupt can be
generated after the read bit. This extra transmit interrupt occurs if
the transmit FIFO is not full.
Figure 60. I
2
C Target Transmit Interrupt Details
In the target, if there is no valid data to transmit when the transmit
shifter is loaded, the transmit underflow status bit asserts (MSTAT,
Bit 12 or SSTAT, Bit 1). In target mode, the transmit FIFO must be
loaded with a byte before the falling edge of I2C_SCL and before
the acknowledge or no acknowledge is asserted. If the transmit
FIFO is empty on the falling edge of I2C_SCL for an R/W bit, the
target returns a no acknowledge because the target in this case
controls the acknowledge or no acknowledge.
If the first byte is transmitted correctly in a target transmit sequence,
but the transmit FIFO is empty for any subsequent bytes in the
same transfer, the target returns the previous transmitted byte. This
operation is due to the initiator having control of the acknowledge
or no acknowledge during a target transfer sequence. The initiator
generates a stop condition if there is no data in the transmit FIFO
and the initiator is writing data.
The receive data path consists of an initiator and target receive
FIFO, the MRX register, and the SRX register. Both are two bytes
deep. The receive request interrupt bit (MSTAT, Bit 3 or SSTAT, Bit
3) indicates whether there is valid data in the receive FIFO. Data
is loaded into the receive FIFO after each byte is received. If valid
data in the receive FIFO is overwritten by the receive shifter, the
receive overflow status bit is asserted (MSTAT, Bit 9 or SSTAT, Bit
4).
Automatic Clock Stretching
The ASTRETCH_SCL register controls automatic clock stretching.
If automatic clock stretching is enabled, the I
2
C hardware holds
the I2C_SCL pin low after the falling edge of I2C_SCL before an
acknowledge or no acknowledge under the following conditions:

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English

Summary

PREFACE

SCOPE

Provides a detailed description of the functionality and features of the ADuCM356.

CLOCKING ARCHITECTURE

DIGITAL DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the digital die system clock.

ANALOG DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the analog die system clock.

POWER MANAGEMENT UNIT

Active Mode

Describes the fully active operating mode where the Arm Cortex-M3 executes from flash and SRAM.

Flexi Mode

Describes the mode where the Arm Cortex-M3 is disabled, allowing peripherals to operate.

Hibernate Mode

Describes the low-power mode where the digital core and most analog blocks are powered down.

SYSTEM RESETS

DIGITAL DIE RESET OPERATION

Explains the reset sources and operation for the digital die, including software resets.

PROGRAMMING, PROTECTION, AND DEBUG

Debug Features

Details the SWD port, flash patch breakpoints, and data watchpoint/trigger units for debugging.

SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS

CORTEX-M3 AND FAULT MANAGEMENT

Describes the system exceptions and fault handling features integrated with the Cortex-M3 processor.

ANALOG DIE CIRCUITRY SUMMARY

ADC, HIGH-SPEED DAC, AND ASSOCIATED AMPLIFIERS OPERATING MODE CONFIGURATION

Configures the operating modes for ADC, High-Speed DAC, and associated amplifiers.

ADC CIRCUIT

ADC CIRCUIT FEATURES

Lists the key features of the ADuCM356's fast multichannel, 16-bit ADC.

LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS

LOW-POWER POTENTIOSTAT AMPLIFIERS

Details the two low-power potentiostat amplifiers for setting external sensor bias voltage.

HIGH-SPEED DAC CIRCUITS

HIGH-SPEED DAC OUTPUT SIGNAL GENERATION

Explains how to generate high-speed DAC output voltage via direct write or waveform generator.

PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH-SPEED DAC AND HIGH-SPEED TIA

DX SWITCHES

Selects pins for the high-speed DAC excitation amplifier output, used for impedance measurements.

SEQUENCER

SEQUENCER COMMANDS

Describes the two types of commands: write commands and timer commands (wait, timeout).

SLEEP AND WAKE-UP TIMER

CONFIGURING A DEFINED SEQUENCE ORDER

Defines the order of sequence execution periodically using the SEQORDER register.

USE CASE CONFIGURATIONS

HIBERNATE MODE WHILE MAINTAINING A DC BIAS TO THE SENSOR

Details setup for hibernate mode while maintaining sensor bias voltage.

DMA CONTROLLER

DMA FEATURES

Lists the features of the ADuCM356's dedicated and independent DMA channels.

FLASH CONTROLLER

SUPPORTED COMMANDS

Summarizes the commands supported by the flash controller for read, write, erase, and signature operations.

REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)

COMMAND REGISTER

Allows execution of specified flash commands like write, erase, abort, and signature generation.

DIGITAL INPUTS AND OUTPUTS

DIGITAL INPUTS AND OUTPUTS OPERATION

Explains how to configure, read, and write digital input and output pins.

I2C SERIAL INTERFACE

I2C OPERATION

Details the steps required to run the I2C peripheral, including startup and modes.

SERIAL PERIPHERAL INTERFACES

SPI OPERATION

Describes the operation of the SPI interface, including initiator and target modes.

REGISTER SUMMARY: SPI0/SPI1

STATUS REGISTERS

Provides status information for SPI0 and SPI1, including ready, overflow, and error conditions.

REGISTER DETAILS: UART

INTERRUPT ENABLE REGISTER

Configures which interrupt sources generate an interrupt for the UART.

DIGITAL DIE GENERAL-PURPOSE TIMERS

GENERAL-PURPOSE TIMER OPERATIONS

Explains the operation of timers in free running mode and periodic mode.

REGISTER SUMMARY: ANALOG DIE GENERAL-PURPOSE TIMERS

CONTROL REGISTER

Controls timer operation, including clock source, mode, and event selection.

REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER

STATUS 0 REGISTER

Provides status information for WUT operation, including synchronization and pending writes.

CYCLIC REDUNDANCY CHECK

CRC OPERATING MODES

Details the core access and DMA access modes for CRC calculation.

REGISTER SUMMARY: CRC

CRC CONTROL REGISTER

Controls the CRC peripheral, including enabling, mirroring, and calculation order.

HARDWARE DESIGN CONSIDERATIONS

SERIAL WIRE DEBUG INTERFACE

Describes the SWD interface for debugging and programming, replacing JTAG.