Reference Manual ADuCM356
I
2
C SERIAL INTERFACE
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â–º The transmit FIFO is empty when a valid read request is active
for the initiator or target.
â–º The receive FIFO is full when another byte is about to be
received. If the receive FIFO has still not been read at the end
of the timeout period, a no acknowledge is returned, and the
initiator ends the sequence with a stop condition.
When enabling automatic clock stretching, enable the timeout fea-
ture to support recovery from incomplete data transfers. A separate
status bit for initiator and target mode indicates if a stretch timeout
has occurred. It is recommended that automatic clock stretching be
enabled, especially in target mode.
If the transmit FIFO is empty on the falling edge of I2C_SCL for
an R/W bit at the end of the timeout period, the target returns a no
acknowledge after the timeout period. If the first byte is transmitted
correctly in a target transmit sequence, but the transmit FIFO is
empty for any subsequent bytes in the same transfer with clock
stretch enabled, the target returns the previous transmitted byte at
the end of the timeout period.
Initiator No Acknowledge
When receiving data, the initiator responds with a no acknowledge
if its FIFO is full and an attempt is made to write another byte to the
FIFO. This last byte received is not written to the FIFO and is lost.
No Acknowledge from the Target
If the target does not want to acknowledge a read access, not writ-
ing data into the target transmit FIFO results in a no acknowledge.
If the target does not want to acknowledge an initiator write, assert
the no acknowledge bit in the target control register, SCTL, Bit 7.
Normally, the target acknowledges all bytes written into the receive
FIFO. If the receive FIFO fills up, the target cannot write further
bytes to it, and the target does not acknowledge subsequent bytes
not written to the FIFO. The initiator must then stop the transaction.
The target does not acknowledge a matching device address if the
R/W bit is set and the transmit FIFO is empty. Therefore, there is
very little time for the microcontroller to respond to a target transmit
request and the assertion of an acknowledge. It is recommended
that SCTL, Bit 5 be asserted for this reason.
General Call
An I
2
C general call is for addressing every device on the I
2
C bus.
A general call address is 0x00 or 0x01. The first byte, the address
byte, is followed by a command byte.
If the address byte is 0x00, Byte 2 (the command byte) can be one
of the following:
â–º 0x6. The I
2
C interface (initiator and target) is reset. The general
call interrupt status asserts, and the general call ID bits, SSTAT,
Bits[9:8], are 0x1. User code must take corrective action to reset
the entire system or simply reenable the I
2
C interface.
â–º 0x4. The general call interrupt status bit is asserted, and the
general call ID bits (SSTAT, Bits[9:8]) are 0x2.
If the address byte is 0x01, a hardware general call is issued. Byte
2 in this case is the hardware initiator address.
The general call interrupt status bit is set on any general call after
the second byte is received, and user code must take corrective
action to reprogram the device address.
If SCTL, Bit 2 is set to 1, the target always acknowledges the first
byte of a general call. The target acknowledges the second byte of
a general call if the second byte is 0x04 or 0x06, or if the second
byte is a hardware general call and SCTL, Bit 3 is set to 1.
The ALT register contains the alternate device ID for a hardware
general call sequence. If the hardware general call enable bit,
the general call enable bit, and the target enable bit are all set
(HGCEN, GCEN, and SLVEN in the SCTL register), the device
recognizes a hardware general call. When a general call sequence
is issued and the second byte of the sequence is identical to the
ALT register, the hardware call sequence is recognized for the
device.
I
2
C Reset Mode
The target state machine is reset when SCTL, Bit 0 is written to 0.
The initiator state machine is reset when MCTL, Bit 0 is written to 0.
I
2
C Test Modes
The device can be placed in an internal loopback mode by setting
MCTL, Bit 2. There are four FIFOs (initiator transmit and receive,
and target transmit and receive). Therefore, the I
2
C peripheral can,
in effect, be set up to communicate with itself. External loopback
can be performed if the initiator is set up to address the target
address.
I
2
C Low-Power Mode
If the initiator and target are both disabled (MCTL, Bit 0 = SCTL,
Bit 0 = 0), the I
2
C section is off. To fully power down the I
2
C block,
disable the clock to the I
2
C section of the chip by setting CTL5, Bit 3
= 1.
Power-Down Considerations
If the initiator or target is idle, they can be immediately disabled by
clearing MCTL, Bit 0 or SCTL, Bit 0 in the initiator or target control
registers, respectively. However, if the initiator or target is active,
there are four possible events occurring and, therefore, four ways to
power down the device, as follows:
â–º I
2
C is an initiator and is receiving data. The device is receiving
data based on the count programmed in the MRXCNT register. It
is in continuous read mode if the MRXCNT, Bit 8 is set. To stop
the read transfer, clear this bit and assign the MRXCNT register
with MCRXCNT, Bits[7:0] + 1, where MCRXCNT, Bits[7:0] give
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