Reference Manual ADuCM356
CACHE
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INITIALIZATION IN CACHE AND INSTRUCTION
SRAM
Enabling the cache provides a significant performance increase
for applications executing from flash. Cache memory coexists with
SRAM. When cache is enabled, part of the SRAM is allocated to
the cache memory, and as such, cache memory cannot be used
for other purposes. Instruction cache size is 4 kB. On wakeup from
hibernation, instruction cache contents are not retained. Instruction
cache is disabled on power-up.
When cache memory is used, parity can also be enabled on its
associated SRAM bank (Bank 5). When SRAM Bank 5 is used
as cache memory, initialization is not required. Initialization is only
required when performing byte or half word accesses to SRAM
with parity check enabled. When SRAM Bank 5 is used as cache
memory, all the accesses are word accesses. Because initialization
is not required for the cache memory, the cache feature is available
immediately following hibernate mode. There is no initialization time
penalty. To prevent undesired bus errors, ignore any initialization of
SRAM Bank 5 when cache is enabled.
As with cache memory, the SRAM banks used as instruction memo-
ry do not require any previous initialization when parity check is en-
abled. Consequently, the instruction SRAM is available immediately
following hibernate mode. If initialization is triggered on instruction
SRAM, it is committed. If instruction SRAM was initialized and an
access to it was received, the access is halted until initialization is
completed.
PROGRAMMING GUIDELINES
The sequence to enable cache is as follows:
1. Read Bit 0 in the FLCC_STAT register to ensure that the cache
is disabled. Poll until this bit is cleared.
2. Write user key to the FLCC key register.
3. Set Bit 0 in the FLCC setup register to enable the cache.
See Table 29 for register details for the SRAM block.
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