Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER
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CONTROL 0 REGISTER
Address: 0x40001400, Reset: 0x03C4, Name: CR0
CR0 is the primary of two control registers for the WUT, the other being CR1. All mainstream WUT operations are enabled and disabled by the
CPU using CR0. The granularity of the WUT control is expanded by the CR1 register.
Table 380. Bit Descriptions for CR0
Bits Bit Name Settings Description Reset Access
15 WPNDINTEN Enable WPENDINT Sourced Interrupts to the CPU. This field is an enable for WUT interrupts to
the CPU, based on the WPENDINT sticky interrupt in the SR0 register.
0x0 R/W
0 Disable WPENDINT sourced interrupts to the CPU.
1 Enable WPENDINT sourced interrupts to the CPU.
14 WSYNCINTEN Enable WSYNCINT Sourced Interrupts to the CPU. WSYNCINTEN is an enable for WUT
interrupts to the CPU based on the WSYNCINT sticky interrupt source field of the SR0 MMR.
WSYNCINTEN is activated whenever the effects of a posted write to a 32 kHz sourced MMR or
MMR bit field become visible to the CPU.
0x0 R/W
0 Disable WSYNCINT sourced interrupts to the CPU.
1 Enable WSYNCINT sourced interrupts to the CPU.
13 WPNDERRINTEN Enable WPNDERRINT Sourced Interrupts to the CPU when a WUT Register Write Pending
Error Occurs. Write pending errors can be avoided by the CPU by checking the pending status
of a register in SR1 before undertaking a write to that register. If a WPNDERRINT error occurs,
and this bit is set to 1, the WUT interrupts the CPU.
0x0 R/W
0 Disable interrupts if write pending errors occur in the WUT.
1 Enable interrupts for write pending errors in the WUT.
12 ISOINTEN Enable ISOINT Sourced Interrupts to the CPU. This bit enables interrupts to the CPU based on
the ISOINT sticky interrupt source in the SR0 status register. When power loss is imminent to
all power domains on the device apart from the WUT, the WUT activates its isolation barrier so
that the WUT can continue to operate independently of the core. When power is subsequently
restored to the rest of the device, the WUT activates the ISOINT interrupt source to act as a
sticky record of the power loss event just finishing. This activation occurs as the WUT lowers its
isolation barrier when the core regains power. If enabled by this bit, the WUT interrupts the CPU
based on ISOINT. The CPU can then inspect the ISOINT field of SR0 to determine if the CPU
has recovered from a total loss of power.
0x0 R/W
0 Disable ISOINT sourced interrupts to the CPU.
1 Enable ISOINT sourced interrupts to the CPU.
11 MOD60ALMINTEN Enable Periodic MOD60ALMINT Sourced Interrupts to the CPU. This bit allows the CPU to
enable a periodic, repeating interrupt from the timer at a displacement time in WUT time units
given by the MOD60ALM bit beyond a Modulo 60 boundary.
0x0 R/W
0 Disable periodic interrupts due to Modulo 60 WUT elapsed time.
1 Enable periodic interrupts due to Modulo 60 WUT elapsed time.
[10:5] MOD60ALM Periodic Modulo 60 Alarm Time in Prescaled WUT Time Units Beyond a Modulo 60 Boundary.
This bit allows the CPU to position a periodic alarm interrupt from the WUT at any integer
number of prescaled WUT time units from a Modulo 60 boundary (roll over event) of the value in
CNT1 and CNT0. Values of 0 to 59 are allowed for MOD60ALM. If a greater value is configured,
this value is treated as zero prescaled WUT time units. Boundaries are defined when the CPU
writes a new pair of values to the CNT1 and CNT0 registers, the CPU enables the WUT from
a disabled state using CR0, Bit 0, or when the WUT is enabled by CR0, Bit 0. For example, a
value of 30 results in the Modulo 60 periodic interrupt from the WUT to be issued to the CPU at
30 time units past a Modulo 60 boundary.
0x1E R/W
4 MOD60ALMEN Enable WUT Modulo 60 Counting of Time Past a Modulo 60 Boundary. Enables the detection
of the counter passing a value of 60, whereas MOD60ALMINTEN enables the generation of a
resultant interrupt.
0x0 R/W
0 Disable determination of Modulo 60 WUT elapsed time.
1 Enable determination of Modulo 60 WUT elapsed time.

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English

Summary

PREFACE

SCOPE

Provides a detailed description of the functionality and features of the ADuCM356.

CLOCKING ARCHITECTURE

DIGITAL DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the digital die system clock.

ANALOG DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the analog die system clock.

POWER MANAGEMENT UNIT

Active Mode

Describes the fully active operating mode where the Arm Cortex-M3 executes from flash and SRAM.

Flexi Mode

Describes the mode where the Arm Cortex-M3 is disabled, allowing peripherals to operate.

Hibernate Mode

Describes the low-power mode where the digital core and most analog blocks are powered down.

SYSTEM RESETS

DIGITAL DIE RESET OPERATION

Explains the reset sources and operation for the digital die, including software resets.

PROGRAMMING, PROTECTION, AND DEBUG

Debug Features

Details the SWD port, flash patch breakpoints, and data watchpoint/trigger units for debugging.

SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS

CORTEX-M3 AND FAULT MANAGEMENT

Describes the system exceptions and fault handling features integrated with the Cortex-M3 processor.

ANALOG DIE CIRCUITRY SUMMARY

ADC, HIGH-SPEED DAC, AND ASSOCIATED AMPLIFIERS OPERATING MODE CONFIGURATION

Configures the operating modes for ADC, High-Speed DAC, and associated amplifiers.

ADC CIRCUIT

ADC CIRCUIT FEATURES

Lists the key features of the ADuCM356's fast multichannel, 16-bit ADC.

LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS

LOW-POWER POTENTIOSTAT AMPLIFIERS

Details the two low-power potentiostat amplifiers for setting external sensor bias voltage.

HIGH-SPEED DAC CIRCUITS

HIGH-SPEED DAC OUTPUT SIGNAL GENERATION

Explains how to generate high-speed DAC output voltage via direct write or waveform generator.

PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH-SPEED DAC AND HIGH-SPEED TIA

DX SWITCHES

Selects pins for the high-speed DAC excitation amplifier output, used for impedance measurements.

SEQUENCER

SEQUENCER COMMANDS

Describes the two types of commands: write commands and timer commands (wait, timeout).

SLEEP AND WAKE-UP TIMER

CONFIGURING A DEFINED SEQUENCE ORDER

Defines the order of sequence execution periodically using the SEQORDER register.

USE CASE CONFIGURATIONS

HIBERNATE MODE WHILE MAINTAINING A DC BIAS TO THE SENSOR

Details setup for hibernate mode while maintaining sensor bias voltage.

DMA CONTROLLER

DMA FEATURES

Lists the features of the ADuCM356's dedicated and independent DMA channels.

FLASH CONTROLLER

SUPPORTED COMMANDS

Summarizes the commands supported by the flash controller for read, write, erase, and signature operations.

REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)

COMMAND REGISTER

Allows execution of specified flash commands like write, erase, abort, and signature generation.

DIGITAL INPUTS AND OUTPUTS

DIGITAL INPUTS AND OUTPUTS OPERATION

Explains how to configure, read, and write digital input and output pins.

I2C SERIAL INTERFACE

I2C OPERATION

Details the steps required to run the I2C peripheral, including startup and modes.

SERIAL PERIPHERAL INTERFACES

SPI OPERATION

Describes the operation of the SPI interface, including initiator and target modes.

REGISTER SUMMARY: SPI0/SPI1

STATUS REGISTERS

Provides status information for SPI0 and SPI1, including ready, overflow, and error conditions.

REGISTER DETAILS: UART

INTERRUPT ENABLE REGISTER

Configures which interrupt sources generate an interrupt for the UART.

DIGITAL DIE GENERAL-PURPOSE TIMERS

GENERAL-PURPOSE TIMER OPERATIONS

Explains the operation of timers in free running mode and periodic mode.

REGISTER SUMMARY: ANALOG DIE GENERAL-PURPOSE TIMERS

CONTROL REGISTER

Controls timer operation, including clock source, mode, and event selection.

REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER

STATUS 0 REGISTER

Provides status information for WUT operation, including synchronization and pending writes.

CYCLIC REDUNDANCY CHECK

CRC OPERATING MODES

Details the core access and DMA access modes for CRC calculation.

REGISTER SUMMARY: CRC

CRC CONTROL REGISTER

Controls the CRC peripheral, including enabling, mirroring, and calculation order.

HARDWARE DESIGN CONSIDERATIONS

SERIAL WIRE DEBUG INTERFACE

Describes the SWD interface for debugging and programming, replacing JTAG.