Reference Manual ADuCM356
UART SERIAL INTERFACE
analog.com Rev. A | 253 of 312
UART OVERVIEW
The UART peripheral is a full duplex UART, compatible with the in-
dustry-standard 16450 UART or 16550 UART. The UART is respon-
sible for converting data between serial and parallel formats. The
serial communication follows an asynchronous protocol, supporting
various word lengths, stop bits, and parity generation options.
This UART also contains interrupt handling hardware. The UART
features a fractional divider that facilitates high accuracy baud rate
generation.
Interrupts can be generated from several unique events, such
as full or empty data buffer, transfer error detection, and break
detection. Modem signals are supported by the UART block, but
these signals are not brought to external pins. The modem signals
are tied off internally.
UART FEATURES
The ADuCM356 features an industry-standard 16450 UART or
16550 UART peripheral with support for DMA.
UART OPERATION
Serial Communications
An asynchronous serial communication protocol is followed with
these options:
â–º 5 data bits to 8 data bits.
â–º 1, 2, or 1.5 stop bits.
â–º None, even, or odd parity.
All data-words require a start bit and at least one stop bit, which
creates a range from 7 bits to 12 bits for each word. Transmit
operation is initiated by writing to the transmit holding register
(COMTX). After a synchronization delay, the data is moved to the
internal transmit shift register, where it is shifted out at a baud (bit)
rate equal to the following equation with start, stop, and parity bits
appended as required:
Baud Rate = PCLK(M + (N/2048) × 2
OSR + 2
× UART_COM-
DIV)
(28)
where:
PCLK is the divided root clock as configured via CNT1, Bits[13:8].
M = 1 to 3 (COMFBR, Bits[12:11]).
N = 0 to 2047 (COMFBR, Bits[10:0]).
UART_COMDIV = 1 to 65,536.
All data-words begin with a low going start bit. The transfer of
COMTX to the transmit shift register causes the transmit register
empty status flag to be set. The receive operation uses the same
data format as the transmit configuration except for the number
of stop bits, which is always one. After detection of the start bit,
the received word is shifted into the internal receive shift register.
After the appropriate number of bits (including stop bits) is received,
the data and any status are updated, and the receive shift register
is transferred to the receive buffer register (COMRX). The receive
buffer register full status flag (COMIIR, Bits[3:1] = 0b010) is updat-
ed upon the transfer of the received word to this buffer and the
appropriate synchronization delay.
A sampling clock equal to 2
OSR
+
2
times the baud rate is used to
sample the data as close to the midpoint of the bit as possible. A
receive filter is also present that removes spurious pulses of less
than two times the sampling clock period. Data is transmitted and
received LSB first.
Programmed Input and Output Mode
In programmed input and output mode, the software is responsible
for moving data to and from the UART. This movement is typically
accomplished by interrupt service routines that respond to the
transmit and receive interrupts by either reading or writing data
as appropriate. This mode puts certain constraints on the software
itself in that the software must respond within a certain time to
prevent overflow errors from occurring in the receive channel.
Polling the status flag is processor intensive and not typically
performed unless the system can tolerate the overhead. Interrupts
can be disabled using the COMIEN register.
Do not write to COMTX when it is not empty or read COMRX when
it is not full, because such actions produce incorrect results. When
COMTX is not empty, COMTX is overwritten by the new word, and
the previous word is never transmitted. When COMRX is not full,
the previously received word is read again. Avoid these errors by
correctly using either interrupts or status register polling. These
errors are not detected in hardware.
Interrupts
The UART peripheral has one interrupt output to the interrupt
controller for both receive and transmit interrupts. The COMIIR
register must be read by the software to determine the cause of the
interrupt. In DMA mode, the break interrupt is not available. When
receiving in input or output mode, the interrupt is generated for the
following cases:
â–º COMRX is full.
â–º Receive overflow error.
â–º Receive parity error.
â–º Receive framing error.
â–º Receive FIFO timeout if FIFO (16550 UART) is enabled.
â–º Break interrupt (UART input pin UART_SIN held low).
â–º COMTX empty.
Buffer Requirements
This UART is double buffered, meaning it has a hold register and a
shift register.
To Next Page
Loading...
Need help?
General