Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
UART SERIAL INTERFACE
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UART OVERVIEW
The UART peripheral is a full duplex UART, compatible with the in-
dustry-standard 16450 UART or 16550 UART. The UART is respon-
sible for converting data between serial and parallel formats. The
serial communication follows an asynchronous protocol, supporting
various word lengths, stop bits, and parity generation options.
This UART also contains interrupt handling hardware. The UART
features a fractional divider that facilitates high accuracy baud rate
generation.
Interrupts can be generated from several unique events, such
as full or empty data buffer, transfer error detection, and break
detection. Modem signals are supported by the UART block, but
these signals are not brought to external pins. The modem signals
are tied off internally.
UART FEATURES
The ADuCM356 features an industry-standard 16450 UART or
16550 UART peripheral with support for DMA.
UART OPERATION
Serial Communications
An asynchronous serial communication protocol is followed with
these options:
► 5 data bits to 8 data bits.
► 1, 2, or 1.5 stop bits.
► None, even, or odd parity.
All data-words require a start bit and at least one stop bit, which
creates a range from 7 bits to 12 bits for each word. Transmit
operation is initiated by writing to the transmit holding register
(COMTX). After a synchronization delay, the data is moved to the
internal transmit shift register, where it is shifted out at a baud (bit)
rate equal to the following equation with start, stop, and parity bits
appended as required:
Baud Rate = PCLK(M + (N/2048) × 2
OSR + 2
× UART_COM-
DIV)
(28)
where:
PCLK is the divided root clock as configured via CNT1, Bits[13:8].
M = 1 to 3 (COMFBR, Bits[12:11]).
N = 0 to 2047 (COMFBR, Bits[10:0]).
UART_COMDIV = 1 to 65,536.
All data-words begin with a low going start bit. The transfer of
COMTX to the transmit shift register causes the transmit register
empty status flag to be set. The receive operation uses the same
data format as the transmit configuration except for the number
of stop bits, which is always one. After detection of the start bit,
the received word is shifted into the internal receive shift register.
After the appropriate number of bits (including stop bits) is received,
the data and any status are updated, and the receive shift register
is transferred to the receive buffer register (COMRX). The receive
buffer register full status flag (COMIIR, Bits[3:1] = 0b010) is updat-
ed upon the transfer of the received word to this buffer and the
appropriate synchronization delay.
A sampling clock equal to 2
OSR + 2
times the baud rate is used to
sample the data as close to the midpoint of the bit as possible. A
receive filter is also present that removes spurious pulses of less
than two times the sampling clock period. Data is transmitted and
received LSB first.
Programmed Input and Output Mode
In programmed input and output mode, the software is responsible
for moving data to and from the UART. This movement is typically
accomplished by interrupt service routines that respond to the
transmit and receive interrupts by either reading or writing data
as appropriate. This mode puts certain constraints on the software
itself in that the software must respond within a certain time to
prevent overflow errors from occurring in the receive channel.
Polling the status flag is processor intensive and not typically
performed unless the system can tolerate the overhead. Interrupts
can be disabled using the COMIEN register.
Do not write to COMTX when it is not empty or read COMRX when
it is not full, because such actions produce incorrect results. When
COMTX is not empty, COMTX is overwritten by the new word, and
the previous word is never transmitted. When COMRX is not full,
the previously received word is read again. Avoid these errors by
correctly using either interrupts or status register polling. These
errors are not detected in hardware.
Interrupts
The UART peripheral has one interrupt output to the interrupt
controller for both receive and transmit interrupts. The COMIIR
register must be read by the software to determine the cause of the
interrupt. In DMA mode, the break interrupt is not available. When
receiving in input or output mode, the interrupt is generated for the
following cases:
► COMRX is full.
► Receive overflow error.
► Receive parity error.
► Receive framing error.
► Receive FIFO timeout if FIFO (16550 UART) is enabled.
► Break interrupt (UART input pin UART_SIN held low).
► COMTX empty.
Buffer Requirements
This UART is double buffered, meaning it has a hold register and a
shift register.

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English

Summary

PREFACE

SCOPE

Provides a detailed description of the functionality and features of the ADuCM356.

CLOCKING ARCHITECTURE

DIGITAL DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the digital die system clock.

ANALOG DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the analog die system clock.

POWER MANAGEMENT UNIT

Active Mode

Describes the fully active operating mode where the Arm Cortex-M3 executes from flash and SRAM.

Flexi Mode

Describes the mode where the Arm Cortex-M3 is disabled, allowing peripherals to operate.

Hibernate Mode

Describes the low-power mode where the digital core and most analog blocks are powered down.

SYSTEM RESETS

DIGITAL DIE RESET OPERATION

Explains the reset sources and operation for the digital die, including software resets.

PROGRAMMING, PROTECTION, AND DEBUG

Debug Features

Details the SWD port, flash patch breakpoints, and data watchpoint/trigger units for debugging.

SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS

CORTEX-M3 AND FAULT MANAGEMENT

Describes the system exceptions and fault handling features integrated with the Cortex-M3 processor.

ANALOG DIE CIRCUITRY SUMMARY

ADC, HIGH-SPEED DAC, AND ASSOCIATED AMPLIFIERS OPERATING MODE CONFIGURATION

Configures the operating modes for ADC, High-Speed DAC, and associated amplifiers.

ADC CIRCUIT

ADC CIRCUIT FEATURES

Lists the key features of the ADuCM356's fast multichannel, 16-bit ADC.

LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS

LOW-POWER POTENTIOSTAT AMPLIFIERS

Details the two low-power potentiostat amplifiers for setting external sensor bias voltage.

HIGH-SPEED DAC CIRCUITS

HIGH-SPEED DAC OUTPUT SIGNAL GENERATION

Explains how to generate high-speed DAC output voltage via direct write or waveform generator.

PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH-SPEED DAC AND HIGH-SPEED TIA

DX SWITCHES

Selects pins for the high-speed DAC excitation amplifier output, used for impedance measurements.

SEQUENCER

SEQUENCER COMMANDS

Describes the two types of commands: write commands and timer commands (wait, timeout).

SLEEP AND WAKE-UP TIMER

CONFIGURING A DEFINED SEQUENCE ORDER

Defines the order of sequence execution periodically using the SEQORDER register.

USE CASE CONFIGURATIONS

HIBERNATE MODE WHILE MAINTAINING A DC BIAS TO THE SENSOR

Details setup for hibernate mode while maintaining sensor bias voltage.

DMA CONTROLLER

DMA FEATURES

Lists the features of the ADuCM356's dedicated and independent DMA channels.

FLASH CONTROLLER

SUPPORTED COMMANDS

Summarizes the commands supported by the flash controller for read, write, erase, and signature operations.

REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)

COMMAND REGISTER

Allows execution of specified flash commands like write, erase, abort, and signature generation.

DIGITAL INPUTS AND OUTPUTS

DIGITAL INPUTS AND OUTPUTS OPERATION

Explains how to configure, read, and write digital input and output pins.

I2C SERIAL INTERFACE

I2C OPERATION

Details the steps required to run the I2C peripheral, including startup and modes.

SERIAL PERIPHERAL INTERFACES

SPI OPERATION

Describes the operation of the SPI interface, including initiator and target modes.

REGISTER SUMMARY: SPI0/SPI1

STATUS REGISTERS

Provides status information for SPI0 and SPI1, including ready, overflow, and error conditions.

REGISTER DETAILS: UART

INTERRUPT ENABLE REGISTER

Configures which interrupt sources generate an interrupt for the UART.

DIGITAL DIE GENERAL-PURPOSE TIMERS

GENERAL-PURPOSE TIMER OPERATIONS

Explains the operation of timers in free running mode and periodic mode.

REGISTER SUMMARY: ANALOG DIE GENERAL-PURPOSE TIMERS

CONTROL REGISTER

Controls timer operation, including clock source, mode, and event selection.

REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER

STATUS 0 REGISTER

Provides status information for WUT operation, including synchronization and pending writes.

CYCLIC REDUNDANCY CHECK

CRC OPERATING MODES

Details the core access and DMA access modes for CRC calculation.

REGISTER SUMMARY: CRC

CRC CONTROL REGISTER

Controls the CRC peripheral, including enabling, mirroring, and calculation order.

HARDWARE DESIGN CONSIDERATIONS

SERIAL WIRE DEBUG INTERFACE

Describes the SWD interface for debugging and programming, replacing JTAG.