Reference Manual ADuCM356
UART SERIAL INTERFACE
analog.com Rev. A | 254 of 312
FIFO Mode (16550 UART)
The 16-byte deep transmit FIFO and receive FIFO are implement-
ed. Therefore, the UART is compatible with the industry-standard
16550 UART. By default, these FIFOs are disabled. To enable
them, set COMFCR, Bit 0. When enabled, the internal FIFOs allow
16 bytes to be stored in both the receive and transmit modes of
operation, and 3 bits of error data per byte in the receive FIFO.
The interrupt and DMA trigger for the number of bytes received
into the receive FIFO is programmed via COMFCR, Bits[7:6]. The
DMA requests are programmed by the COMFCR, Bit 3. If this bit
is set, the FIFO must also be enabled by setting COMFCR, Bit 0
to 1. If the remaining bytes in a packet are less than the interrupt
trigger number, a timeout interrupt occurs. This timeout is indicated
by COMIIR, Bits[3:1] = 0b110. This timeout period is equal to the
period of four consecutive characters where a single character time
is one start bit, n data bits, one parity bit, and one stop bit, where n
depends on the word length selected by COMLCR, Bits[1:0].
DMA Mode
In DMA mode, user code does not move data to and from the
UART. DMA request signals entering the external DMA block indi-
cate that the UART is ready to transmit or receive data. These DMA
request signals can be disabled in the COMIEN register.
Automatic Baud Rate Detection
The automatic baud detection (ABD) block is used to match the
baud rates of two UART devices automatically. The receiver must
be enabled to detect the mode before a common baud rate is
configured. The COMACR, Bit 0 enables the receiver to work in
ABD mode. A 20-bit counter logic counts the number of cycles
between the programmed rising or falling edge and another rising
or falling edge. An interrupt is generated after the expected edges
are reached. The counter can overflow and generate a timeout
interrupt, such as when there is a continuous break condition or no
expected edges.
For example, if the data byte being received is 0x0D (0b00001101,
resulting in a carriage return) in 8-bit mode without a parity bit, LSB
first, each bit reads as DATA0 = 1, DATA1 = 0, DATA2 = 1, DATA3 =
1, and DATA4 = DATA5 = DATA6 = DATA7 = 0.
There are three falling edges and three rising edges. The CO-
MACR, Bits[6:4] can be written to 1 decimal (second edge), and
COMACR, Bits[11:8] can be written to 5 decimal (sixth edge) to
count between the first rising edge and the second rising edge. See
Figure 63 for more details.
Figure 63. Autobaud Rate Example
Similarly, for 0x7F (0b01111111, the ASCII DEL value delete key),
COMACR, Bits[6:4] = 1 and COMACR, Bits[11:8] = 3 to count
between the first rising edge and the second rising edge. Automatic
baud rate must be disabled to clear the internal counter and reena-
bled for another sequence (if required). Based on the UART baud
rate configuration, the ABD result can be calculated as follows:
CNT, Bits[19:0] = CountedBits × 2OSR + 2 × COMDIV × (COMFBR,
Bits[12:11] + COMFBR, Bits[10:0]/2048)
where:
CountedBits is the effective number of bits between an active
starting edge and ending edge. It is determined by the application
code on the selected edges and character used for ABD.
COMDIV is calculated as follows:
If CNT, Bits[19:0] < 8 × CountedBits, then OSR = 0, COMDIV =
1, and COMFBR, Bits[10:0] = 512 × CNT, Bits[19:0]/CountedBits −
2048.
If CNT, Bits[19:0] < 16 × CountedBits, then OSR = 1, COMDIV =
1, and COMFBR, Bits[10:0] = 256 × CNT, Bits[19:0]/CountedBits −
2048.
If CNT, Bits[19:0] < 32 × CountedBits, then OSR = 2, COMDIV =
1, and COMFBR, Bits[10:0] = 128 × CNT, Bits[19:0]/CountedBits −
2048.
If CNT, Bits[19:0] ≥ 32 × CountedBits, then OSR = 3.
If CNT, Bits[19:0] is exactly divided by 32 × CountedBits, then
COMDIV = (CNT, Bits[19:0]/32)/CountedBits.
Otherwise, COMDIV = 2log
2
((CNT[19:0]/32)/CountedBits) and
COMFBR, Bits[10:0] = (((64 × CNT, Bits[19:0])/COMDIV)/ Counted-
Bits) − 2048.
To reduce truncation error, the DIVM field (COMFBR, Bits[12:11]) is
set to 1. The DIV field (COMDIV, Bits[15:0]) is set to the nearest
power of 2. COMASRH, Bits[7:0] and COMASRL, Bits[15:4] make
up CNT, Bits[19:0].
Clock Gating
The clock driving the UART logic is automatically gated off when
idle, and not accessed. This automatic clock gating cannot be
disabled by COMCTL, Bit 1.
To Next Page
Loading...
Need help?
General