Reference Manual ADuCM356
SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS
analog.com Rev. A | 42 of 312
if (uiIntSta & BITM_AFE_ADCINTSTA_ADCRDY)
{
szADCSamples[i]= AfeAdcRd(RAWADC);
}
}
CLEARING ANALOG DIE INTERRUPT
SOURCES
IRQ48, IRQ52, IRQ54, IRQ55, and IRQ57 are interrupt sources
from the analog die.
Ensure that the interrupt is fully serviced and the associated inter-
rupt status flags are fully cleared before exiting the interrupt service
routine. If user code exits the interrupt service routine before the
interrupt flag is fully cleared, the CPU program counter can repeat-
edly vector back into the same interrupt service routine.
In the case of timer interrupts, add a short delay of 30
AFE_SYSCLK periods after clearing the timeout status bit but
before exiting the timer interrupt service routine.
The following is an example interrupt service routine for the Analog
Die General-Purpose Timer 0:
// AFE General-Purpose Timer0 Interrupt hanâ–º
dler.
void AfeGpTimer0_Int_Handler()
{
ucSecondTimer = 1;
pADI_AGPT0->CLRI0 =
0x1; // Clear Timeout IRQ
delay(100); // Enâ–º
sure the delay equates to 10 >=30x analog die
System clocks
}
CORTEX-M3 NVIC REGISTER LIST
The registers in Table 43 are found in the Arm Cortex-M3.
Table 43. NVIC Registers
Address
Analog Devices
Header File Name Description Access
0xE000E004 ICTR Shows the number of interrupt lines that the NVIC supports. R
0xE000E010 STCSR System tick timer control and status. R/W
0xE000E014 STRVR System tick timer reload value. R/W
0xE000E018 STCVR System tick timer current value. R/W
0xE000E01C STCR System tick timer calibration value. R
0xE000E100 ISER0 Set IRQ0 to IRQ31 enable. Each bit corresponds to IRQ0 to IRQ31 in Table 41. R/W
0xE000E104 ISER1 Set IRQ32 to IRQ63 enable. Each bit corresponds to IRQ32 to IRQ63 in Table 41. R/W
0xE000E180 ICER0 Clear IRQ0 to IRQ31 by setting the appropriate bit. Each bit corresponds to IRQ0 to IRQ31 in Table 41. R/W
0xE000E184 ICER1 Clear IRQ32 to IRQ63 by setting the appropriate bit. Each bit corresponds to IRQ32 to IRQ63 in Table 41. R/W
0xE000E200 ISPR0 Set IRQ0 to IRQ31 pending. Each bit corresponds to IRQ0 to IRQ31 in Table 41. R/W
0xE000E204 ISPR1 Set IRQ32 to IRQ63 pending. Each bit corresponds to IRQ32 to IRQ63 in Table 41. R/W
0xE000E280 ICPR0 Clear IRQ0 to IRQ31 pending. Each bit corresponds to IRQ0 to IRQ31 in Table 41. R/W
0xE000E284 ICPR1 Clear IRQ32 to IRQ63 pending. Each bit corresponds to IRQ32 to IRQ63 in Table 41. R/W
0xE000E300 IABR0 IRQ0 to IRQ31 active bits. R/W
0xE000E304 IABR1 IRQ32 to IRQ63 active bits. R/W
0xE000E400 IPR0 IRQ0 to IRQ3 priority. R/W
0xE000E404 IPR1 IRQ4 to IRQ7 priority. R/W
0xE000E408 IPR2 IRQ8 to IRQ11 priority. R/W
0xE000E40C IPR3 IRQ12 to IRQ15 priority. R/W
0xE000E410 IPR4 IRQ16 to IRQ19 priority. R/W
0xE000E414 IPR5 IRQ20 to IRQ23 priority. R/W
0xE000E418 IPR6 IRQ24 to IRQ27 priority. R/W
0xE000E41C IPR7 IRQ28 to IRQ31 priority. R/W
0xE000E420 IPR8 IRQ32 to IRQ35 priority. R/W
0xE000E424 IPR9 IRQ36 to IRQ39 priority. R/W
0xE000E428 IPR10 IRQ40 to IRQ43 priority. R/W
0xE000E42C IPR11 IRQ44 to IRQ47 priority. R/W
0xE000E430 IPR12 IRQ48 to IRQ51 priority. R/W
0xE000E434 IPR13 IRQ52 to IRQ55 priority. R/W
To Next Page
Loading...
Need help?
General