Reference Manual ADuCM356
REGISTER DETAILS: ANALOG DIE GENERAL-PURPOSE TIMERS
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Table 362. Bit Descriptions for INTEN
Bits Bit Name Settings Description Reset Access
[15:1] Reserved Reserved. 0x0 R
0 INTEN Interrupt Enable. This value is used when the PWM is operating in match mode. The PWM output is
asserted when the up or down counter is equal to this match value. PWM output is deasserted again
when a timeout event occurs. If the match value is never reached, or occurs simultaneous to a timeout
event, the PWM output remains idle.
0x0 R/W
16-BIT LOAD VALUE REGISTER
Address: 0x400C0E00, Reset: 0x0000, Name: LOAD
Table 363. Bit Descriptions for LOAD
Bits Bit Name Settings Description Reset Access
[15:0] VALUE Load Value. The up or down counter is periodically loaded with this value if periodic mode is selected
(CTL, Bit 3 = 1). Writes from this bit during up or down counter timeout events are delayed until the event
has passed.
0x0 R/W
16-BIT TIMER VALUE REGISTER
Address: 0x400C0E04, Reset: 0x0000, Name: CURCNT
Table 364. Bit Descriptions for CURCNT
Bits Bit Name Settings Description Reset Access
[15:0] VALUE Current Count. Reflects the current up or down counter value. Value delayed two PCLK cycles due to
clock synchronizers.
0x0 R
CONTROL REGISTER
Address: 0x400C0E08, Reset: 0x000A, Name: CTL
Table 365. Bit Descriptions for CTL
Bits Bit Name Settings Description Reset Access
15 SYNCBYP Synchronization Bypass. Used to bypass the synchronization logic within the block. Use only with
synchronous clocks. This bit field also changes the PRE bit maximum prescaler count from 3 to 0.
0x0 R/W
14 RSTEN Counter and Prescale Reset Enable. Used to enable and disable the reset feature. Used in conjunction
with CTL, Bit 13 (EVTEN) and CTL, Bits[12:8] (EVTRANGE). When a selected event occurs, the 16-bit
counter and 8-bit prescale are reset. This reset is required in PWM demodulation mode.
0x0 R/W
13 EVTEN Event Select. Used to enable and disable the capture of events. Used in conjunction with the CTL,
Bits[12:8] (EVTRANGE) bits. When a selected event occurs, the current value of the up or down counter
is captured in GPTx_CAPTURE.
0x0 R/W
0 Events are not captured.
1 Events are captured.
[12:8] EVTRANGE Event Select Range. Timer event select range (0 to 31). 0x0 R/W
7 RLD Reload Control. This bit is only used for periodic mode. This bit allows the user to select whether the up
or down counter is reset only on a timeout event or also when CLRINT, Bit 0 is set.
0x0 R/W
1 Resets the up or down counter when the clear timeout interrupt bit is set.
0 Up or down counter is only reset on a timeout event.
[6:5] CLK Clock Select. Used to select a timer clock from the four available clock sources. 0x0 R/W
00 AFE PCLK.
01 AFE high-power oscillator.
10 AFE low frequency oscillator.
11 External clock.
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