Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
DIGITAL DIE WAKE-UP TIMER
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OVERVIEW
The digital die WUT is the highest priority interrupt on the
ADuCM356, as described in Table 41. The WUT is also one of
four interrupt sources that can wake the digital die from hibernate
mode. The WUT is clocked by the low frequency oscillator. The
accuracy specifications of the low frequency oscillator deem this
timer unsuitable for a real-time clock setup, although some register
names indicate support for a true real-time clock. Because the WUT
is clocked by the 32 kHz oscillator, take care when performing CPU
reads or writes to the wake-up timer registers. Synchronization
status bits are provided to indicate when a read or write access is
fully complete in the 32 kHz domain.
FEATURES
Key digital die WUT features include the following:
► 32 kHz input clock can be further divided by a prescale factor of
2
0
to 2
15
.
► The timer count register is nominally a 32-bit value configured
by the 16-bit registers, CNT1 and CNT0, for total Bits[31:0]. This
value can be expanded to 47 bits if CNT2 (the fractional divide
register) is used, enabling CNT1, CNT0, and CNT2 for Bits[46:0].
When initializing or reenabling the WUT count, or when changing
the prescale division ratio, the prescaler is automatically zeroed
so that the WUT count value is positioned on exact, coincident
boundaries of both the start of the prescale sequence and the
modulo 60 count roll over.
► The WUT block can generate interrupts from multiple sources,
unmasked by programming the CR0 register. The source of the
interrupt is reflected in the SR0 register. The timer interrupt sour-
ces include two optionally enabled, independent alarm features
(one at absolute time and the other at modulo 60 periodic time)
that cause a processor interrupt when the timer count equals the
alarm values.
► The WUT can take and preserve a snapshot of its elapsed real
time count when prompted to do so by the CPU, allowing the
CPU to associate a time stamp with an incoming data packet.
The WUT preserves the snapshot for readback by the CPU. The
snapshot is persistent and is only overwritten when the CPU
issues a request to capture a new value.
REGULAR AND PERIODIC MODULO 60
INTERRUPTS
To enable periodic interrupts, the modulo 60 feature of the timer can
be used. The modulo block divides the timer counter by 60 if the
remainder modulus equals the value in CR0, Bits[10:5] or a modulo
alarm or interrupt occurs.
To enable periodic interrupts, perform the following steps:
1. Select the timer prescale value by writing to CR1, Bits[8:5]. This
setting configures the base clock frequency for the timer.
2. Poll the WSYNCCR0 bit and wait for it to be set in the SR0
register as the MMR write occurs in the slower RTC domain.
3. Select the number of counts after 0 for the interrupt to occur.
Write a value between 0 and 59 to CR0, Bits[10:5].
4. Enable the MOD60ALMINTEN interrupt source. Set CR0, Bit 11
= 1.
5. Enable modulo 60 alarms. Set CR0, Bit 4 = 1.
6. Set the global enable bit for the timer by setting CR0, Bit 0 = 1
to start the timer.
TIMER MATCHING ALARM VALUE
INTERRUPTS
The WUT generates an interrupt when the timer counter value
matches the value set by the user in the alarm registers, CNT1
and CNT0, for Bits[31:0], or the alarm registers, CNT1, CNT0, and
CNT2, for Bits[46:0]. To program this interrupt, perform the following
steps:
1. Reset the CNTx registers to 0.
2. Configure the prescaler to divide the WUT base clock in the
CR1 register.
3. Poll the WSYNCCR0 bit and wait for the bit to be set in the SR0
register as the MMR write occurs in the slower WUT domain.
4. Program the ALM0 register, ALM1 register, RTC register, and
ALM2 register with the intended alarm time.
5. Enable the interrupt for alarm by setting CR0, Bit 2.
6. Set the ALMEN and CNTEN bits in the CR0 register.
7. Wait for the WUT alarm interrupt, which is triggered when the
CNTx register value matches the ALMx register value.
WUT FUNCTIONAL DESCRIPTION
A high level block diagram of the WUT is shown in Figure 65. All
functionality for counting, alarm, snapshot, and wake-up interrupts
is located in a dedicated 32 kHz, timed, always on WUT power
domain. The APB interface with the CPU (which comprises queuing
and dispatch logic for posted register writes) and interrupts to the
Cortex NVIC are located in a PCLK and FCLK timed section of the
main power gated core domain.

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English

Summary

PREFACE

SCOPE

Provides a detailed description of the functionality and features of the ADuCM356.

CLOCKING ARCHITECTURE

DIGITAL DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the digital die system clock.

ANALOG DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the analog die system clock.

POWER MANAGEMENT UNIT

Active Mode

Describes the fully active operating mode where the Arm Cortex-M3 executes from flash and SRAM.

Flexi Mode

Describes the mode where the Arm Cortex-M3 is disabled, allowing peripherals to operate.

Hibernate Mode

Describes the low-power mode where the digital core and most analog blocks are powered down.

SYSTEM RESETS

DIGITAL DIE RESET OPERATION

Explains the reset sources and operation for the digital die, including software resets.

PROGRAMMING, PROTECTION, AND DEBUG

Debug Features

Details the SWD port, flash patch breakpoints, and data watchpoint/trigger units for debugging.

SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS

CORTEX-M3 AND FAULT MANAGEMENT

Describes the system exceptions and fault handling features integrated with the Cortex-M3 processor.

ANALOG DIE CIRCUITRY SUMMARY

ADC, HIGH-SPEED DAC, AND ASSOCIATED AMPLIFIERS OPERATING MODE CONFIGURATION

Configures the operating modes for ADC, High-Speed DAC, and associated amplifiers.

ADC CIRCUIT

ADC CIRCUIT FEATURES

Lists the key features of the ADuCM356's fast multichannel, 16-bit ADC.

LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS

LOW-POWER POTENTIOSTAT AMPLIFIERS

Details the two low-power potentiostat amplifiers for setting external sensor bias voltage.

HIGH-SPEED DAC CIRCUITS

HIGH-SPEED DAC OUTPUT SIGNAL GENERATION

Explains how to generate high-speed DAC output voltage via direct write or waveform generator.

PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH-SPEED DAC AND HIGH-SPEED TIA

DX SWITCHES

Selects pins for the high-speed DAC excitation amplifier output, used for impedance measurements.

SEQUENCER

SEQUENCER COMMANDS

Describes the two types of commands: write commands and timer commands (wait, timeout).

SLEEP AND WAKE-UP TIMER

CONFIGURING A DEFINED SEQUENCE ORDER

Defines the order of sequence execution periodically using the SEQORDER register.

USE CASE CONFIGURATIONS

HIBERNATE MODE WHILE MAINTAINING A DC BIAS TO THE SENSOR

Details setup for hibernate mode while maintaining sensor bias voltage.

DMA CONTROLLER

DMA FEATURES

Lists the features of the ADuCM356's dedicated and independent DMA channels.

FLASH CONTROLLER

SUPPORTED COMMANDS

Summarizes the commands supported by the flash controller for read, write, erase, and signature operations.

REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)

COMMAND REGISTER

Allows execution of specified flash commands like write, erase, abort, and signature generation.

DIGITAL INPUTS AND OUTPUTS

DIGITAL INPUTS AND OUTPUTS OPERATION

Explains how to configure, read, and write digital input and output pins.

I2C SERIAL INTERFACE

I2C OPERATION

Details the steps required to run the I2C peripheral, including startup and modes.

SERIAL PERIPHERAL INTERFACES

SPI OPERATION

Describes the operation of the SPI interface, including initiator and target modes.

REGISTER SUMMARY: SPI0/SPI1

STATUS REGISTERS

Provides status information for SPI0 and SPI1, including ready, overflow, and error conditions.

REGISTER DETAILS: UART

INTERRUPT ENABLE REGISTER

Configures which interrupt sources generate an interrupt for the UART.

DIGITAL DIE GENERAL-PURPOSE TIMERS

GENERAL-PURPOSE TIMER OPERATIONS

Explains the operation of timers in free running mode and periodic mode.

REGISTER SUMMARY: ANALOG DIE GENERAL-PURPOSE TIMERS

CONTROL REGISTER

Controls timer operation, including clock source, mode, and event selection.

REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER

STATUS 0 REGISTER

Provides status information for WUT operation, including synchronization and pending writes.

CYCLIC REDUNDANCY CHECK

CRC OPERATING MODES

Details the core access and DMA access modes for CRC calculation.

REGISTER SUMMARY: CRC

CRC CONTROL REGISTER

Controls the CRC peripheral, including enabling, mirroring, and calculation order.

HARDWARE DESIGN CONSIDERATIONS

SERIAL WIRE DEBUG INTERFACE

Describes the SWD interface for debugging and programming, replacing JTAG.