Reference Manual ADuCM356
FLASH CONTROLLER
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Read of Erased Location
When erased, the flash memory holds a value of all 1s, including the ECC byte appended to every 6-bit data word. The proper ECC metadata
for 64 1s is not 0xFF. As such, in its erased state, the flash memory holds data and ECC metadata representing some number of bit errors. For
this reason, any flash reads of erased locations automatically bypass the ECC engine. If user code reads a location with all 1s in both the 64-bit
data word and the ECC byte, the read returns data without indicating any ECC errors.
CLOCK AND TIMINGS
The flash controller is preconfigured to provide safe timing parame-
ters for all flash operations for core clock frequencies of 26 MHz or
less, and a reference clock frequency of 13 MHz.
FLASH OPERATING MODES
The flash memory used by the ADuCM356 processor supports the
following power optimizing features.
Sleep Mode
The user code can put the flash IP into a low-power sleep mode by
writing the sleep command to the CMD register. The flash controller
wakes the flash IP from sleep automatically on the first flash access
following a sleep command. The user code can observe the sleep
state of flash by reading STAT, Bit 6.
A flash wake-up event is triggered by the cache controller, DMA
reads, user code, or other peripherals, which may also attempt to
read flash memory at any time. Ensure that user code occasionally
polls STAT, Bit 6 to verify that the flash IP is still sleeping when the
user expects it to be.
The flash controller does not honor any new commands while
the flash IP is in sleep mode. The only supported commands
in this mode are idle and abort. DMA write requests are stalled
automatically by entering sleep mode.
System interrupt-based aborts (as configured through the
ABORT_EN_LO register) are generally used to abort any ongoing
flash commands in the event of an enabled system interrupt. How-
ever, such an interrupt does not wake the flash from sleep mode.
If the system interrupt can be serviced by accessing the flash, it
remains in sleep mode. If servicing the interrupt requires accessing
the flash, the flash access itself serves to wake the flash IP.
Waking from sleep incurs an approximately 5 μs latency before
executing any reads or commands. This latency is a requirement of
the flash IP. User code can wake the flash IP early by executing an
idle command. This command wakes the flash IP without any other
effect on the controller.
For consistency, the abort command can also be used to wake the
flash IP. Waking with the abort command differs from waking by the
idle command only in that the status register reports STAT, Bits[5:4]
= 11 to match expected user code checks for status register values.
Power-Down Mode Support
The ADuCM356 processor automatically powers down the flash
IP when the device hibernates. To support this feature, the flash
controller operates with the power management unit and delays
hibernation until any ongoing flash accesses are completed. User
code is responsible for reading and evaluating flash status registers
prior to entering hibernate mode because status registers are not
retained in hibernate mode. The abort command can be used to
abruptly end an ongoing flash command. Use abort commands
sparingly to avoid eventual damage to the flash array.
Clock Gating
A series of clock gates are inserted into the flash controller to
automatically gate off unused components of the module. No user
configuration or control is required. Unused portions of the flash
controller are automatically gated off when appropriate. For exam-
ple, while in sleep mode, the majority of the flash controller is gated
off to save power.
Flash Interrupts and Exceptions
The flash controller can selectively generate interrupts for many
events. Table 222 outlines the events that may generate interrupts
and bit fields of the IEN register used to control interrupt generation
for each event.
Table 222. Interrupts and Bit Fields
Name (Bit Field) Description
ECC_ERROR IRQ is generated when 2-bit ECC errors are observed and when this field is set to 2.
ECC_CORRECT IRQ is generated when 1-bit ECC corrections are observed and when this field is set to 2.
CMDFAIL IRQ generated when a command or write operation completes with an error status.
WRALCMPLT IRQ generated when an active flash write is nearly complete and the keyhole registers are open for another write. If fulfilled in time, a burst write
occurs.
CMDCMPLT IRQ generated when a command or flash write operation completes.
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