Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
REGISTER DETAILS: SPI0/SPI1
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Table 306. Bit Descriptions for SPI0_STAT, SPI1_STAT (Continued)
Bits Bit Name Settings Description Reset Access
2 TXEMPTY SPI Transmit FIFO Empty Interrupt. 0x0 R/W1C
0 Cleared to 0 when 1 is written to this bit or when SPIx_CTL, Bit 0 is cleared to 0.
1 Set when the transmit FIFO is empty. This bit generates an interrupt if SPIx_IEN, Bit 14 is set to 1 except
when SPIx_CTL, Bit 13 is set.
1 XFRDONE SPI Transfer Completion. This bit indicates the status of SPI transfer completion in initiator mode. 0x0 R/W1C
0 Cleared to 0 when 1 is written to this bit.
1 Set when the transfer of SPIx_CNT, Bits[13:0] number of bytes has finished. In target mode or if
SPIx_CNT, Bits[13:0] = 0, this bit is invalid. If SPIx_IENx, Bit 13 is set, this bit generates an interrupt. It
uses the state of the initiator state machine to determine the completion of a SPI transfer. Therefore, a
chip select override does not affect this bit.
0 IRQ SPI Interrupt Status. 0x0 R
0 Cleared to 0 when all SPI interrupt sources are cleared.
1 Set when an SPI based interrupt occurs.
RECEIVE REGISTERS
Address: 0x40004004, Reset: 0x0000, Name: SPI0_RX
Address: 0x40024004, Reset: 0x0000, Name: SPI1_RX
Table 307. Bit Descriptions for SPI0_RX, SPI1_RX
Bits Bit Name Settings Description Reset Access
[15:8] BYTE2 8-Bit Receive Buffer. These 8 bits are used only in DMA mode, where all FIFO accesses occur as half word
accesses. They return 0 if DMA is disabled.
0x0 R
[7:0] BYTE1 8-Bit Receive Buffer. 0x0 R
TRANSMIT REGISTERS
Address: 0x40004008, Reset: 0x0000, Name: SPI0_TX
Address: 0x40024008, Reset: 0x0000, Name: SPI1_TX
Table 308. Bit Descriptions for SPI0_TX, SPI1_TX
Bits Bit Name Settings Description Reset Access
[15:8] BYTE2 8-Bit Transmit Buffer. These 8 bits are used only in DMA mode, where all FIFO accesses occur as half
word accesses. They return 0 if DMA is disabled.
0x0 W
[7:0] BYTE1 8-Bit Transmit Buffer. 0x0 W
BAUD RATE SELECTION REGISTERS
Address: 0x4000400C, Reset: 0x0000, Name: SPI0_DIV
Address: 0x4002400C, Reset: 0x0000, Name: SPI1_DIV
Table 309. Bit Descriptions for SPI0_DIV, SPI1_DIV
Bits Bit Name Settings Description Reset Access
[15:6] Reserved Reserved. 0x0 R
[5:0] VALUE SPI Clock Divider. The clock divider value is the factor used to divide UCLK to generate the serial clock. 0x0 R/W
CONFIGURATION REGISTERS
Address: 0x40004010, Reset: 0x0000, Name: SPI0_CTL
Address: 0x40024010, Reset: 0x0000, Name: SPI1_CTL

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English

Summary

PREFACE

SCOPE

Provides a detailed description of the functionality and features of the ADuCM356.

CLOCKING ARCHITECTURE

DIGITAL DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the digital die system clock.

ANALOG DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the analog die system clock.

POWER MANAGEMENT UNIT

Active Mode

Describes the fully active operating mode where the Arm Cortex-M3 executes from flash and SRAM.

Flexi Mode

Describes the mode where the Arm Cortex-M3 is disabled, allowing peripherals to operate.

Hibernate Mode

Describes the low-power mode where the digital core and most analog blocks are powered down.

SYSTEM RESETS

DIGITAL DIE RESET OPERATION

Explains the reset sources and operation for the digital die, including software resets.

PROGRAMMING, PROTECTION, AND DEBUG

Debug Features

Details the SWD port, flash patch breakpoints, and data watchpoint/trigger units for debugging.

SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS

CORTEX-M3 AND FAULT MANAGEMENT

Describes the system exceptions and fault handling features integrated with the Cortex-M3 processor.

ANALOG DIE CIRCUITRY SUMMARY

ADC, HIGH-SPEED DAC, AND ASSOCIATED AMPLIFIERS OPERATING MODE CONFIGURATION

Configures the operating modes for ADC, High-Speed DAC, and associated amplifiers.

ADC CIRCUIT

ADC CIRCUIT FEATURES

Lists the key features of the ADuCM356's fast multichannel, 16-bit ADC.

LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS

LOW-POWER POTENTIOSTAT AMPLIFIERS

Details the two low-power potentiostat amplifiers for setting external sensor bias voltage.

HIGH-SPEED DAC CIRCUITS

HIGH-SPEED DAC OUTPUT SIGNAL GENERATION

Explains how to generate high-speed DAC output voltage via direct write or waveform generator.

PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH-SPEED DAC AND HIGH-SPEED TIA

DX SWITCHES

Selects pins for the high-speed DAC excitation amplifier output, used for impedance measurements.

SEQUENCER

SEQUENCER COMMANDS

Describes the two types of commands: write commands and timer commands (wait, timeout).

SLEEP AND WAKE-UP TIMER

CONFIGURING A DEFINED SEQUENCE ORDER

Defines the order of sequence execution periodically using the SEQORDER register.

USE CASE CONFIGURATIONS

HIBERNATE MODE WHILE MAINTAINING A DC BIAS TO THE SENSOR

Details setup for hibernate mode while maintaining sensor bias voltage.

DMA CONTROLLER

DMA FEATURES

Lists the features of the ADuCM356's dedicated and independent DMA channels.

FLASH CONTROLLER

SUPPORTED COMMANDS

Summarizes the commands supported by the flash controller for read, write, erase, and signature operations.

REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)

COMMAND REGISTER

Allows execution of specified flash commands like write, erase, abort, and signature generation.

DIGITAL INPUTS AND OUTPUTS

DIGITAL INPUTS AND OUTPUTS OPERATION

Explains how to configure, read, and write digital input and output pins.

I2C SERIAL INTERFACE

I2C OPERATION

Details the steps required to run the I2C peripheral, including startup and modes.

SERIAL PERIPHERAL INTERFACES

SPI OPERATION

Describes the operation of the SPI interface, including initiator and target modes.

REGISTER SUMMARY: SPI0/SPI1

STATUS REGISTERS

Provides status information for SPI0 and SPI1, including ready, overflow, and error conditions.

REGISTER DETAILS: UART

INTERRUPT ENABLE REGISTER

Configures which interrupt sources generate an interrupt for the UART.

DIGITAL DIE GENERAL-PURPOSE TIMERS

GENERAL-PURPOSE TIMER OPERATIONS

Explains the operation of timers in free running mode and periodic mode.

REGISTER SUMMARY: ANALOG DIE GENERAL-PURPOSE TIMERS

CONTROL REGISTER

Controls timer operation, including clock source, mode, and event selection.

REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER

STATUS 0 REGISTER

Provides status information for WUT operation, including synchronization and pending writes.

CYCLIC REDUNDANCY CHECK

CRC OPERATING MODES

Details the core access and DMA access modes for CRC calculation.

REGISTER SUMMARY: CRC

CRC CONTROL REGISTER

Controls the CRC peripheral, including enabling, mirroring, and calculation order.

HARDWARE DESIGN CONSIDERATIONS

SERIAL WIRE DEBUG INTERFACE

Describes the SWD interface for debugging and programming, replacing JTAG.