Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)
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Table 232. Bit descriptions for KEY (Continued)
Bits Bit Name Settings Description Reset Access
0x676C7565 User key. Write this field with hexadecimal value of 0x676C7565 to enable certain registers to be
modified or to allow certain commands to be executed. This key is used as a check to prevent
accidental modification of settings or flash content. It is not a security component and is not intended
to be confidential information.
WRITE ABORT ADDRESS REGISTER
Address: 0x40018024, Reset: 0xXXXXXXXX, Name: WR_ABORT_ADDR
This register contains the address of a recently aborted write command. This address is only populated if the aborted write command was
started. If the command is aborted early enough to have no effect on the flash IP, this address is not updated.
Table 233. Bit Descriptions for WR_ABORT_ADDR
Bits Bit Name Settings Description Reset Access
[31:0] VALUE Hold Target Address. Holds the address targeted by an ongoing write command and retains
its value after an abort event. User code can read this register to determine the flash locations
affected by a write abort. The register value is not guaranteed to persist after a new flash
command is requested. Therefore, read this value immediately following an aborted write.
0xXXXXXXXX R
WRITE PROTECTION REGISTER
Address: 0x40018028, Reset: 0xFFFFFFFF, Name: WRPROT
A user key is required to modify this register. This register can be automatically configured during device startup, in which case the bootloader
reads data from user space and loads that data into this register.
User code can affect nonvolatile write protection by writing to the appropriate location in the flash memory (see the Protection and Integrity
section). By default, the relevant location in flash is 0x0019C but can be relocated by the Analog Devices bootloader.
Alternatively, user code can assert protection at run time for any unprotected blocks by directly writing this register. Blocks can have
protection added but cannot have protection removed, and changes are lost on reset. This approach is suggested especially during user code
development.
All write protection is cleared on a POR, but the Analog Devices bootloader reasserts write protection (as defined by the WRPROT word) in
user space before enabling user access to the flash array. Removing write protection can only be performed by an erase page command of the
most significant page in user space (provided that page is not currently protected) or by a mass erase command. Following a completed mass
erase command, all protection of pages in user space is immediately cleared. The user can write to user space immediately following such an
erase without a device reset required.
Table 234. Bit Descriptions for WRPROT
Bits Bit Name Settings Description Reset Access
[31:0] WORD Clear Bits to Write Protect Related Groups of User Space Pages. After cleared, these bits can
only be set again by resetting the device. Each bit of this 32-bit word represents a 32nd of the
total available user space. For 256 kB parts consisting of 2 kB pages (128 pages), each bit
represents the write protection state of a group of four pages. The most significant bit of this
register corresponds to the most significant group of pages in user space.
0xFFFFFFFF R/W0C
SIGNATURE REGISTER
Address: 0x4001802C, Reset: 0xXXXXXXXX, Name: SIGNATURE
Table 235. Bit Descriptions for SIGNATURE
Bits Bit Name Settings Description Reset Access
[31:0] VALUE Provides Read Access to the Most Recently Generated Signature. 0xXXXXXXXX R

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English

Summary

PREFACE

SCOPE

Provides a detailed description of the functionality and features of the ADuCM356.

CLOCKING ARCHITECTURE

DIGITAL DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the digital die system clock.

ANALOG DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the analog die system clock.

POWER MANAGEMENT UNIT

Active Mode

Describes the fully active operating mode where the Arm Cortex-M3 executes from flash and SRAM.

Flexi Mode

Describes the mode where the Arm Cortex-M3 is disabled, allowing peripherals to operate.

Hibernate Mode

Describes the low-power mode where the digital core and most analog blocks are powered down.

SYSTEM RESETS

DIGITAL DIE RESET OPERATION

Explains the reset sources and operation for the digital die, including software resets.

PROGRAMMING, PROTECTION, AND DEBUG

Debug Features

Details the SWD port, flash patch breakpoints, and data watchpoint/trigger units for debugging.

SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS

CORTEX-M3 AND FAULT MANAGEMENT

Describes the system exceptions and fault handling features integrated with the Cortex-M3 processor.

ANALOG DIE CIRCUITRY SUMMARY

ADC, HIGH-SPEED DAC, AND ASSOCIATED AMPLIFIERS OPERATING MODE CONFIGURATION

Configures the operating modes for ADC, High-Speed DAC, and associated amplifiers.

ADC CIRCUIT

ADC CIRCUIT FEATURES

Lists the key features of the ADuCM356's fast multichannel, 16-bit ADC.

LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS

LOW-POWER POTENTIOSTAT AMPLIFIERS

Details the two low-power potentiostat amplifiers for setting external sensor bias voltage.

HIGH-SPEED DAC CIRCUITS

HIGH-SPEED DAC OUTPUT SIGNAL GENERATION

Explains how to generate high-speed DAC output voltage via direct write or waveform generator.

PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH-SPEED DAC AND HIGH-SPEED TIA

DX SWITCHES

Selects pins for the high-speed DAC excitation amplifier output, used for impedance measurements.

SEQUENCER

SEQUENCER COMMANDS

Describes the two types of commands: write commands and timer commands (wait, timeout).

SLEEP AND WAKE-UP TIMER

CONFIGURING A DEFINED SEQUENCE ORDER

Defines the order of sequence execution periodically using the SEQORDER register.

USE CASE CONFIGURATIONS

HIBERNATE MODE WHILE MAINTAINING A DC BIAS TO THE SENSOR

Details setup for hibernate mode while maintaining sensor bias voltage.

DMA CONTROLLER

DMA FEATURES

Lists the features of the ADuCM356's dedicated and independent DMA channels.

FLASH CONTROLLER

SUPPORTED COMMANDS

Summarizes the commands supported by the flash controller for read, write, erase, and signature operations.

REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)

COMMAND REGISTER

Allows execution of specified flash commands like write, erase, abort, and signature generation.

DIGITAL INPUTS AND OUTPUTS

DIGITAL INPUTS AND OUTPUTS OPERATION

Explains how to configure, read, and write digital input and output pins.

I2C SERIAL INTERFACE

I2C OPERATION

Details the steps required to run the I2C peripheral, including startup and modes.

SERIAL PERIPHERAL INTERFACES

SPI OPERATION

Describes the operation of the SPI interface, including initiator and target modes.

REGISTER SUMMARY: SPI0/SPI1

STATUS REGISTERS

Provides status information for SPI0 and SPI1, including ready, overflow, and error conditions.

REGISTER DETAILS: UART

INTERRUPT ENABLE REGISTER

Configures which interrupt sources generate an interrupt for the UART.

DIGITAL DIE GENERAL-PURPOSE TIMERS

GENERAL-PURPOSE TIMER OPERATIONS

Explains the operation of timers in free running mode and periodic mode.

REGISTER SUMMARY: ANALOG DIE GENERAL-PURPOSE TIMERS

CONTROL REGISTER

Controls timer operation, including clock source, mode, and event selection.

REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER

STATUS 0 REGISTER

Provides status information for WUT operation, including synchronization and pending writes.

CYCLIC REDUNDANCY CHECK

CRC OPERATING MODES

Details the core access and DMA access modes for CRC calculation.

REGISTER SUMMARY: CRC

CRC CONTROL REGISTER

Controls the CRC peripheral, including enabling, mirroring, and calculation order.

HARDWARE DESIGN CONSIDERATIONS

SERIAL WIRE DEBUG INTERFACE

Describes the SWD interface for debugging and programming, replacing JTAG.