Reference Manual ADuCM356
REGISTER DETAILS: CLOCK ARCHITECTURE
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Table 13. Bit Descriptions for CLKSEL (Continued)
Bits Bit Name Settings Description Reset Access
1 External high frequency crystal (XTAL) clock.
10 Internal low frequency oscillator clock. Not recommended.
11 External clock.
[1:0] SYSCLKSEL Select System Clock Source. To configure the GPIO1 pin for an external clock, 0x0 R/W
pADI_AGPIO2->CON |= 3<<2; // EXT_CLK pADI_AGPIO2->IEN |=
1<<1; //AGPIO2.1(PWM1) input
0 Internal high frequency oscillator clock.
1 External high frequency XTAL clock.
10 Internal low frequency oscillator clock. Not recommended.
11 External clock.
GPIO CLOCK MUX SELECT TO GPIO1 PIN REGISTER
Address: 0x400C041C, Reset: 0x0000, Name: GPIOCLKMUXSEL
Select which digital clock is output to GPIO1 for observation.
Table 14. Bit Descriptions for GPIOCLKMUXSEL
Bits Bit Name Settings Description Reset Access
[15:3] Reserved Reserved. 0x0 R
[2:0] SEL Configure Clock Mux Out to GPIO1. 0x0 R/W
0 System clock.
1 Power gate low frequency clock.
10 PCLK.
11 Wake-up timer (WUT) on analog die clock.
100 GPT0 clock.
101 GPT1 clock.
110 ADC clock.
111 ADC control clock.
KEY PROTECTION FOR CLKCON0 REGISTER
Address: 0x400C0420, Reset: 0x0000, Name: CLKCON0KEY
This register provides key protection for the CLKCON0 register.
Table 15. Bit Descriptions for CLKCON0KEY
Bits Bit Name Settings Description Reset Access
[15:0] KEY Key to Allow Read and Write Access to the CLKCON0 Register. Write 0xA815 to this register before
accessing CLKCON0.
0x0 W
CLOCK CONTROL OF LOW-POWER TIA CHOP, WATCHDOG, AND WAKE-UP TIMERS REGISTER
Address: 0x400C0A70, Reset: 0x0000, Name: CLKEN0
Table 16. Bit Descriptions for CLKEN0
Bits Bit Name Settings Description Reset Access
[15:3] Reserved Reserved. 0x0 R
2 TIACHPDIS TIA Chop Clock Disable. 0x1 R/W
0 Turn on TIA chop clock.
1 Turn off TIA chop clock.
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