Reference Manual ADuCM356
REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)
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Table 226. Bit Descriptions for CMD (Continued)
Bits Bit Name Settings Description Reset Access
flash. It is always advisable to erase the affected region and reprogram it. Depending on how far along the
flash controller is in the process of performing a command, an abort is not always possible. Some flash
IP timing parameters must not be violated. It is difficult to predict what these parameters are in software.
Therefore, consider aborts to be a request that may have no effect on actual command duration.
0x2 Requests flash to enter sleep mode. User key is required. When sleeping, any ICode, DCode, or DMA
transaction wakes the flash automatically. The wake-up process takes approximately 5 μs. If user code can
predict approximately 5 μs ahead of time that the flash is required, the user can write an idle command to
the CMD register to manually wake the flash. An abort command is also respected for waking the device
and returns the appropriate status bits, indicating that the sleep command was aborted. When awoken for
any reason, the device remains awake until user code asserts a sleep command.
0x3 Sign. User key is required. Use this command to generate a signature for a block of data. Signatures can
be generated for blocks of whole pages only. Write the address of the start page to the PAGE_ADDR0
register, write the address of the end page to the PAGE_ADDR1 register, and then write this code to
the CMD register to start the signature generation. When the command has completed, the signature is
readable from the signature register.
0x4 Write. No key is required. This command takes the address and data from the KH_ADDR register,
KH_DATA0 register, and KH_DATA1 register and executes a single 64-bit write operation targeting the
specified address. More information can be found in the Writing Flash section and the Write Protection
Register section.
0x5 Checks all user space and fails if any bits in user space are cleared. User key is required. Performs a blank
check on all user space. If any bits in user space are cleared, the command fails with a read verify status.
If all of user space is 0xFF, the command passes. This command is intended to support early customer
software development. When an unprogrammed device boots with security features preventing reads and
writes of user space, this command can be used to verify that the user space contains no proprietary
information. If this command passes, read and write protection of user space is cleared.
0x6 Erase page. User key is required. Write the address of the page to be erased to the PAGE_ADDR0
register, then write this code to the CMD register. When the erase has completed, the full page is verified
automatically to ensure a complete erasure. If there is a read verify error, it is indicated in the STAT
register. To erase multiple pages, wait until a previous page erase has completed. Check the status, then
issue a command to start the next page erase.
0x7 Mass erase. User key is required. Erase all of flash user space. When the erase has completed, the
full user space is verified automatically to ensure a complete erasure. If there is a read verify error, it is
indicated in the status register.
WRITE ADDRESS REGISTER
Address: 0x4001800C, Reset: 0x00000000, Name: KH_ADDR
This register writes the byte address of any byte of a 64-bit, dual-word flash location to be targeted by a write command. All writes target 64-bit,
dual-word elements in the flash array. User code can mask byte data to emulate byte, half word, or word writes. Flash IP specifications warn
against writing to any location more than twice between erasures. When writing a location more than once, be aware that ECC metadata cannot
be updated appropriately. Use code to disable ECC for the relevant region of flash. Writing any address above the valid range of flash memory
saturates the address to prevent aliasing. Take care to target valid flash address locations.
Table 227. Bit Descriptions for KH_ADDR
Bits Bit Name Settings Description Reset Access
[31:19] Reserved Reserved. 0x0 R
[18:3] VALUE Address to Be Written on a Write Command. 0x0 R/W
[2:0] Reserved Reserved. 0x0 R
WRITE LOWER DATA REGISTER
Address: 0x40018010, Reset: 0xFFFFFFFF, Name: KH_DATA0
This register contains the lower half of 64-bit dual-word data to be written to flash.
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