Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)
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Table 226. Bit Descriptions for CMD (Continued)
Bits Bit Name Settings Description Reset Access
flash. It is always advisable to erase the affected region and reprogram it. Depending on how far along the
flash controller is in the process of performing a command, an abort is not always possible. Some flash
IP timing parameters must not be violated. It is difficult to predict what these parameters are in software.
Therefore, consider aborts to be a request that may have no effect on actual command duration.
0x2 Requests flash to enter sleep mode. User key is required. When sleeping, any ICode, DCode, or DMA
transaction wakes the flash automatically. The wake-up process takes approximately 5 μs. If user code can
predict approximately 5 μs ahead of time that the flash is required, the user can write an idle command to
the CMD register to manually wake the flash. An abort command is also respected for waking the device
and returns the appropriate status bits, indicating that the sleep command was aborted. When awoken for
any reason, the device remains awake until user code asserts a sleep command.
0x3 Sign. User key is required. Use this command to generate a signature for a block of data. Signatures can
be generated for blocks of whole pages only. Write the address of the start page to the PAGE_ADDR0
register, write the address of the end page to the PAGE_ADDR1 register, and then write this code to
the CMD register to start the signature generation. When the command has completed, the signature is
readable from the signature register.
0x4 Write. No key is required. This command takes the address and data from the KH_ADDR register,
KH_DATA0 register, and KH_DATA1 register and executes a single 64-bit write operation targeting the
specified address. More information can be found in the Writing Flash section and the Write Protection
Register section.
0x5 Checks all user space and fails if any bits in user space are cleared. User key is required. Performs a blank
check on all user space. If any bits in user space are cleared, the command fails with a read verify status.
If all of user space is 0xFF, the command passes. This command is intended to support early customer
software development. When an unprogrammed device boots with security features preventing reads and
writes of user space, this command can be used to verify that the user space contains no proprietary
information. If this command passes, read and write protection of user space is cleared.
0x6 Erase page. User key is required. Write the address of the page to be erased to the PAGE_ADDR0
register, then write this code to the CMD register. When the erase has completed, the full page is verified
automatically to ensure a complete erasure. If there is a read verify error, it is indicated in the STAT
register. To erase multiple pages, wait until a previous page erase has completed. Check the status, then
issue a command to start the next page erase.
0x7 Mass erase. User key is required. Erase all of flash user space. When the erase has completed, the
full user space is verified automatically to ensure a complete erasure. If there is a read verify error, it is
indicated in the status register.
WRITE ADDRESS REGISTER
Address: 0x4001800C, Reset: 0x00000000, Name: KH_ADDR
This register writes the byte address of any byte of a 64-bit, dual-word flash location to be targeted by a write command. All writes target 64-bit,
dual-word elements in the flash array. User code can mask byte data to emulate byte, half word, or word writes. Flash IP specifications warn
against writing to any location more than twice between erasures. When writing a location more than once, be aware that ECC metadata cannot
be updated appropriately. Use code to disable ECC for the relevant region of flash. Writing any address above the valid range of flash memory
saturates the address to prevent aliasing. Take care to target valid flash address locations.
Table 227. Bit Descriptions for KH_ADDR
Bits Bit Name Settings Description Reset Access
[31:19] Reserved Reserved. 0x0 R
[18:3] VALUE Address to Be Written on a Write Command. 0x0 R/W
[2:0] Reserved Reserved. 0x0 R
WRITE LOWER DATA REGISTER
Address: 0x40018010, Reset: 0xFFFFFFFF, Name: KH_DATA0
This register contains the lower half of 64-bit dual-word data to be written to flash.

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English

Summary

PREFACE

SCOPE

Provides a detailed description of the functionality and features of the ADuCM356.

CLOCKING ARCHITECTURE

DIGITAL DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the digital die system clock.

ANALOG DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the analog die system clock.

POWER MANAGEMENT UNIT

Active Mode

Describes the fully active operating mode where the Arm Cortex-M3 executes from flash and SRAM.

Flexi Mode

Describes the mode where the Arm Cortex-M3 is disabled, allowing peripherals to operate.

Hibernate Mode

Describes the low-power mode where the digital core and most analog blocks are powered down.

SYSTEM RESETS

DIGITAL DIE RESET OPERATION

Explains the reset sources and operation for the digital die, including software resets.

PROGRAMMING, PROTECTION, AND DEBUG

Debug Features

Details the SWD port, flash patch breakpoints, and data watchpoint/trigger units for debugging.

SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS

CORTEX-M3 AND FAULT MANAGEMENT

Describes the system exceptions and fault handling features integrated with the Cortex-M3 processor.

ANALOG DIE CIRCUITRY SUMMARY

ADC, HIGH-SPEED DAC, AND ASSOCIATED AMPLIFIERS OPERATING MODE CONFIGURATION

Configures the operating modes for ADC, High-Speed DAC, and associated amplifiers.

ADC CIRCUIT

ADC CIRCUIT FEATURES

Lists the key features of the ADuCM356's fast multichannel, 16-bit ADC.

LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS

LOW-POWER POTENTIOSTAT AMPLIFIERS

Details the two low-power potentiostat amplifiers for setting external sensor bias voltage.

HIGH-SPEED DAC CIRCUITS

HIGH-SPEED DAC OUTPUT SIGNAL GENERATION

Explains how to generate high-speed DAC output voltage via direct write or waveform generator.

PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH-SPEED DAC AND HIGH-SPEED TIA

DX SWITCHES

Selects pins for the high-speed DAC excitation amplifier output, used for impedance measurements.

SEQUENCER

SEQUENCER COMMANDS

Describes the two types of commands: write commands and timer commands (wait, timeout).

SLEEP AND WAKE-UP TIMER

CONFIGURING A DEFINED SEQUENCE ORDER

Defines the order of sequence execution periodically using the SEQORDER register.

USE CASE CONFIGURATIONS

HIBERNATE MODE WHILE MAINTAINING A DC BIAS TO THE SENSOR

Details setup for hibernate mode while maintaining sensor bias voltage.

DMA CONTROLLER

DMA FEATURES

Lists the features of the ADuCM356's dedicated and independent DMA channels.

FLASH CONTROLLER

SUPPORTED COMMANDS

Summarizes the commands supported by the flash controller for read, write, erase, and signature operations.

REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)

COMMAND REGISTER

Allows execution of specified flash commands like write, erase, abort, and signature generation.

DIGITAL INPUTS AND OUTPUTS

DIGITAL INPUTS AND OUTPUTS OPERATION

Explains how to configure, read, and write digital input and output pins.

I2C SERIAL INTERFACE

I2C OPERATION

Details the steps required to run the I2C peripheral, including startup and modes.

SERIAL PERIPHERAL INTERFACES

SPI OPERATION

Describes the operation of the SPI interface, including initiator and target modes.

REGISTER SUMMARY: SPI0/SPI1

STATUS REGISTERS

Provides status information for SPI0 and SPI1, including ready, overflow, and error conditions.

REGISTER DETAILS: UART

INTERRUPT ENABLE REGISTER

Configures which interrupt sources generate an interrupt for the UART.

DIGITAL DIE GENERAL-PURPOSE TIMERS

GENERAL-PURPOSE TIMER OPERATIONS

Explains the operation of timers in free running mode and periodic mode.

REGISTER SUMMARY: ANALOG DIE GENERAL-PURPOSE TIMERS

CONTROL REGISTER

Controls timer operation, including clock source, mode, and event selection.

REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER

STATUS 0 REGISTER

Provides status information for WUT operation, including synchronization and pending writes.

CYCLIC REDUNDANCY CHECK

CRC OPERATING MODES

Details the core access and DMA access modes for CRC calculation.

REGISTER SUMMARY: CRC

CRC CONTROL REGISTER

Controls the CRC peripheral, including enabling, mirroring, and calculation order.

HARDWARE DESIGN CONSIDERATIONS

SERIAL WIRE DEBUG INTERFACE

Describes the SWD interface for debugging and programming, replacing JTAG.