Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
REGISTER DETAILS: SPI0/SPI1
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Table 310. Bit Descriptions for SPI0_CTL, SPI1_CTL (Continued)
Bits Bit Name Settings Description Reset Access
1 Serial clock pulses at the beginning of each serial bit transfer.
1 MASEN Initiator Mode Enable. 0x0 R/W
0 Enable target mode.
1 Enable initiator mode.
0 SPIEN SPI Enable. 0x0 R/W
0 Disable the SPI.
1 Enable the SPI.
INTERRUPT CONFIGURATION REGISTERS
Address: 0x40004014, Reset: 0x0000, Name: SPI0_IEN
Address: 0x40024014, Reset: 0x0000, Name: SPI1_IEN
Table 311. Bit Descriptions for SPI0_IEN, SPI1_IEN
Bits Bit Name Settings Description Reset Access
15 Reserved Reserved. 0x0 R
14 TXEMPTY Transmit FIFO Empty Interrupt Enable. This bit enables the SPIx_STAT, Bit 2 interrupt whenever the transmit
FIFO is emptied.
0x0 R/W
0 TXEMPTY interrupt is disabled.
1 TXEMPTY interrupt is enabled.
13 XFRDONE SPI Transfer Completion Interrupt Enable. This bit enables the SPIx_STAT, Bit 1 interrupt. 0x0 R/W
0 XFRDONE interrupt is disabled.
1 XFRDONE interrupt is enabled.
12 TXDONE SPI Transmit Done Interrupt Enable. This bit enables the SPIx_STAT, Bit 3 interrupt in read command mode.
This interrupt can be used to signal the change of SPI transfer direction in read command mode.
0x0 R/W
0 TXDONE interrupt is disabled.
1 TXDONE interrupt is enabled.
11 RDY Ready Signal Edge Interrupt Enable. This bit enables the SPIx_STAT, Bit 15 interrupt whenever an active
edge occurs on P0.3 signals. If SPIx_FLOW_CTL, Bits[1:0] = 0b10, this bit is set whenever an active edge is
detected on the P0.3 signal. If SPIx_FLOW_CTL, Bits[1:0] = 0b11, this bit is set if an active edge is detected
on the MISO signal. If SPIx_FLOW_CTL, Bits[1:0] = 0b00 or 0b01, this bit is always 0. The active edge
(rising or falling) is determined by SPIx_FLOW_CTL, Bit 4.
0x0 R/W
0 Ready signal edge interrupt is disabled.
1 Ready signal edge interrupt is enabled.
10 RXOVR Receive Overflow Interrupt Enable. 0x0 R/W
0 Receive overflow interrupt is disabled.
1 Receive overflow interrupt is enabled.
9 TXUNDR Transmit Underflow Interrupt Enable. 0x0 R/W
0 Transmit underflow interrupt is disabled.
1 Transmit underflow interrupt is enabled.
8 CS Enable Interrupt on Every Chip Select Edge in Target Continuous Mode. 0x0 R/W
0 No interrupt is generated and the status bits are not asserted.
1 If the SPI module is configured as a target in continuous mode, any edge on chip select generates an
interrupt and the corresponding status bits (SPIx_STAT, Bit 14 and SPIx_STAT, Bit 13) are asserted. This bit
has no effect if the SPI is not in continuous mode or if it is an initiator.
[7:3] Reserved Reserved. 0x0 R
[2:0] IRQMODE SPI IRQ Mode Bits. These bits configure when the transmit or receive interrupts occur in a transfer. For DMA
receive transfer, these bits are 0b000.
0x0 R/W
000 Transmit interrupt occurs when 1 byte has been transferred. Receive interrupt occurs when 1 or more bytes
have been received into the FIFO.

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English

Summary

PREFACE

SCOPE

Provides a detailed description of the functionality and features of the ADuCM356.

CLOCKING ARCHITECTURE

DIGITAL DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the digital die system clock.

ANALOG DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the analog die system clock.

POWER MANAGEMENT UNIT

Active Mode

Describes the fully active operating mode where the Arm Cortex-M3 executes from flash and SRAM.

Flexi Mode

Describes the mode where the Arm Cortex-M3 is disabled, allowing peripherals to operate.

Hibernate Mode

Describes the low-power mode where the digital core and most analog blocks are powered down.

SYSTEM RESETS

DIGITAL DIE RESET OPERATION

Explains the reset sources and operation for the digital die, including software resets.

PROGRAMMING, PROTECTION, AND DEBUG

Debug Features

Details the SWD port, flash patch breakpoints, and data watchpoint/trigger units for debugging.

SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS

CORTEX-M3 AND FAULT MANAGEMENT

Describes the system exceptions and fault handling features integrated with the Cortex-M3 processor.

ANALOG DIE CIRCUITRY SUMMARY

ADC, HIGH-SPEED DAC, AND ASSOCIATED AMPLIFIERS OPERATING MODE CONFIGURATION

Configures the operating modes for ADC, High-Speed DAC, and associated amplifiers.

ADC CIRCUIT

ADC CIRCUIT FEATURES

Lists the key features of the ADuCM356's fast multichannel, 16-bit ADC.

LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS

LOW-POWER POTENTIOSTAT AMPLIFIERS

Details the two low-power potentiostat amplifiers for setting external sensor bias voltage.

HIGH-SPEED DAC CIRCUITS

HIGH-SPEED DAC OUTPUT SIGNAL GENERATION

Explains how to generate high-speed DAC output voltage via direct write or waveform generator.

PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH-SPEED DAC AND HIGH-SPEED TIA

DX SWITCHES

Selects pins for the high-speed DAC excitation amplifier output, used for impedance measurements.

SEQUENCER

SEQUENCER COMMANDS

Describes the two types of commands: write commands and timer commands (wait, timeout).

SLEEP AND WAKE-UP TIMER

CONFIGURING A DEFINED SEQUENCE ORDER

Defines the order of sequence execution periodically using the SEQORDER register.

USE CASE CONFIGURATIONS

HIBERNATE MODE WHILE MAINTAINING A DC BIAS TO THE SENSOR

Details setup for hibernate mode while maintaining sensor bias voltage.

DMA CONTROLLER

DMA FEATURES

Lists the features of the ADuCM356's dedicated and independent DMA channels.

FLASH CONTROLLER

SUPPORTED COMMANDS

Summarizes the commands supported by the flash controller for read, write, erase, and signature operations.

REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)

COMMAND REGISTER

Allows execution of specified flash commands like write, erase, abort, and signature generation.

DIGITAL INPUTS AND OUTPUTS

DIGITAL INPUTS AND OUTPUTS OPERATION

Explains how to configure, read, and write digital input and output pins.

I2C SERIAL INTERFACE

I2C OPERATION

Details the steps required to run the I2C peripheral, including startup and modes.

SERIAL PERIPHERAL INTERFACES

SPI OPERATION

Describes the operation of the SPI interface, including initiator and target modes.

REGISTER SUMMARY: SPI0/SPI1

STATUS REGISTERS

Provides status information for SPI0 and SPI1, including ready, overflow, and error conditions.

REGISTER DETAILS: UART

INTERRUPT ENABLE REGISTER

Configures which interrupt sources generate an interrupt for the UART.

DIGITAL DIE GENERAL-PURPOSE TIMERS

GENERAL-PURPOSE TIMER OPERATIONS

Explains the operation of timers in free running mode and periodic mode.

REGISTER SUMMARY: ANALOG DIE GENERAL-PURPOSE TIMERS

CONTROL REGISTER

Controls timer operation, including clock source, mode, and event selection.

REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER

STATUS 0 REGISTER

Provides status information for WUT operation, including synchronization and pending writes.

CYCLIC REDUNDANCY CHECK

CRC OPERATING MODES

Details the core access and DMA access modes for CRC calculation.

REGISTER SUMMARY: CRC

CRC CONTROL REGISTER

Controls the CRC peripheral, including enabling, mirroring, and calculation order.

HARDWARE DESIGN CONSIDERATIONS

SERIAL WIRE DEBUG INTERFACE

Describes the SWD interface for debugging and programming, replacing JTAG.