Reference Manual ADuCM356
REGISTER DETAILS: SPI0/SPI1
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Table 310. Bit Descriptions for SPI0_CTL, SPI1_CTL (Continued)
Bits Bit Name Settings Description Reset Access
1 Serial clock pulses at the beginning of each serial bit transfer.
1 MASEN Initiator Mode Enable. 0x0 R/W
0 Enable target mode.
1 Enable initiator mode.
0 SPIEN SPI Enable. 0x0 R/W
0 Disable the SPI.
1 Enable the SPI.
INTERRUPT CONFIGURATION REGISTERS
Address: 0x40004014, Reset: 0x0000, Name: SPI0_IEN
Address: 0x40024014, Reset: 0x0000, Name: SPI1_IEN
Table 311. Bit Descriptions for SPI0_IEN, SPI1_IEN
Bits Bit Name Settings Description Reset Access
15 Reserved Reserved. 0x0 R
14 TXEMPTY Transmit FIFO Empty Interrupt Enable. This bit enables the SPIx_STAT, Bit 2 interrupt whenever the transmit
FIFO is emptied.
0x0 R/W
0 TXEMPTY interrupt is disabled.
1 TXEMPTY interrupt is enabled.
13 XFRDONE SPI Transfer Completion Interrupt Enable. This bit enables the SPIx_STAT, Bit 1 interrupt. 0x0 R/W
0 XFRDONE interrupt is disabled.
1 XFRDONE interrupt is enabled.
12 TXDONE SPI Transmit Done Interrupt Enable. This bit enables the SPIx_STAT, Bit 3 interrupt in read command mode.
This interrupt can be used to signal the change of SPI transfer direction in read command mode.
0x0 R/W
0 TXDONE interrupt is disabled.
1 TXDONE interrupt is enabled.
11 RDY Ready Signal Edge Interrupt Enable. This bit enables the SPIx_STAT, Bit 15 interrupt whenever an active
edge occurs on P0.3 signals. If SPIx_FLOW_CTL, Bits[1:0] = 0b10, this bit is set whenever an active edge is
detected on the P0.3 signal. If SPIx_FLOW_CTL, Bits[1:0] = 0b11, this bit is set if an active edge is detected
on the MISO signal. If SPIx_FLOW_CTL, Bits[1:0] = 0b00 or 0b01, this bit is always 0. The active edge
(rising or falling) is determined by SPIx_FLOW_CTL, Bit 4.
0x0 R/W
0 Ready signal edge interrupt is disabled.
1 Ready signal edge interrupt is enabled.
10 RXOVR Receive Overflow Interrupt Enable. 0x0 R/W
0 Receive overflow interrupt is disabled.
1 Receive overflow interrupt is enabled.
9 TXUNDR Transmit Underflow Interrupt Enable. 0x0 R/W
0 Transmit underflow interrupt is disabled.
1 Transmit underflow interrupt is enabled.
8 CS Enable Interrupt on Every Chip Select Edge in Target Continuous Mode. 0x0 R/W
0 No interrupt is generated and the status bits are not asserted.
1 If the SPI module is configured as a target in continuous mode, any edge on chip select generates an
interrupt and the corresponding status bits (SPIx_STAT, Bit 14 and SPIx_STAT, Bit 13) are asserted. This bit
has no effect if the SPI is not in continuous mode or if it is an initiator.
[7:3] Reserved Reserved. 0x0 R
[2:0] IRQMODE SPI IRQ Mode Bits. These bits configure when the transmit or receive interrupts occur in a transfer. For DMA
receive transfer, these bits are 0b000.
0x0 R/W
000 Transmit interrupt occurs when 1 byte has been transferred. Receive interrupt occurs when 1 or more bytes
have been received into the FIFO.
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