Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
REGISTER DETAILS: POWER MANAGEMENT UNIT
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Table 29. Bit Descriptions for SRAM_CTL (Continued)
Bits Bit Name Settings Description Reset Access
16 PENBNK0 Enable Parity Check for SRAM Bank 0. SRAM Address 0x20000000 to Address 0x20001FFF. Parity is
checked when data is read and when a byte or half word data is written to this SRAM area. If a parity
error is detected, a bus error is generated and the execution vectors to the bus fault interrupt.
0x0 R/W
0 Disable parity check of this bank of SRAM.
1 Enable parity check of this bank of SRAM.
15 ABTINIT Abort Current Initialization. Self cleared. 0x0 R/W
14 AUTOINIT Automatic Initialization on Wake-Up from Hibernate Mode. 0x0 R/W
13 STARTINIT Write One to Trigger Initialization. Self cleared. 0x0 R/W
[12:6] RESERVED Reserved. 0x00 R
5 BNK5EN Enable Initialization of SRAM Bank 5. 0x0 R/W
0 Disable initialization of this bank of SRAM.
1 Enable initialization of this bank of SRAM.
4 BNK4EN Enable Initialization of SRAM Bank 4. 0x0 R/W
0 Disable initialization of this bank of SRAM.
1 Enable initialization of this bank of SRAM.
3 BNK3EN Enable Initialization of SRAM Bank 3. 0x0 R/W
0 Disable initialization of this bank of SRAM.
1 Enable initialization of this bank of SRAM.
2 BNK2EN Enable Initialization of SRAM Bank 2. SRAM Address 0x10000000 to Address 0x10003FFF if
SRAM_CTL, Bit 31 = 1. Address range is 0x20004000 to 0x20007FFF if SRAM_CTL, Bit 31 = 0.
Initialization is necessary on exiting hibernate mode if the SRAM is not retained and parity checking is
enabled.
0x0 R/W
0 Disable initialization of this bank of SRAM.
1 Enable initialization of this bank of SRAM.
1 BNK1EN Enable Initialization of SRAM Bank 1. SRAM Address 0x20002000 to Address 0x20003FFF. Initialization
is necessary on exiting hibernate mode if the SRAM is not retained and parity checking is enabled.
0x0 R/W
0 Disable initialization of this bank of SRAM.
1 Enable initialization of this bank of SRAM.
0 BNK0EN Enable Initialization of SRAM Bank 0. SRAM Address 0x20000000 to Address 0x20001FFF. Initialization
is necessary on exiting hibernate mode if the SRAM is not retained and parity checking is enabled.
0x0 R/W
0 Disable initialization of this bank of SRAM.
1 Enable initialization of this bank of SRAM.
INITIALIZATION STATUS REGISTER
Address: 0x4004C264, Reset: 0x00000001, Name: SRAM_INITSTAT
Table 30. Bit Descriptions for SRAM_INITSTAT
Bits Bit Name Settings Description Reset Access
[31:6] Reserved Reserved. 0x0000000 R/W
5 BNK5 Initialization Status of SRAM Bank 5. 0x0 R
0 Not initialized.
1 Initialization completed.
4 BNK4 Initialization Status of SRAM Bank 4. 0x0 R
0 Not initialized.
1 Initialization completed.
3 BNK3 Initialization Status of SRAM Bank 3. R
0 Not initialized. 0x0
1 Initialization completed.
2 BNK2 Initialization Status of SRAM Bank 2. 0x0 R

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English