Reference Manual ADuCM356
REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER
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ALARM 1 REGISTER
Address: 0x40001418, Reset: 0xFFFF, Name: ALM1
ALM1 contains the upper 16 bits of the prescaled nonfractional WUT alarm target time value, where the overall alarm is defined as ALM1,
ALM0, and ALM2.
Any write to ALM1 pends until corresponding writes to ALM0 and ALM2 are carried out by the CPU, so that the combined 47-bit alarm
redefinition can be executed as a single transaction. ALM0, ALM1, and ALM2 can be written in any order, but coordinated, triple writes must
be carried out by the CPU to have any effect on the WUT alarm. ALM1 can be written to regardless of whether the ALMEN or CNTEN bits are
active in the CR0 register.
Table 386. Bit Descriptions for ALM1
Bits Bit Name Settings Description Reset Access
[15:0] VALUE Upper 16 Prescaled Nonfractional Bits of the WUT Alarm Target Time. The alarm register has a different
reset value to the WUT count to avoid spurious alarms.
0xFFFF R/W
GATEWAY REGISTER
Address: 0x40001420, Reset: 0x0000, Name: GWY
GWY is a gateway MMR address through which the CPU can order actions to be taken within the WUT. The CPU does this by writing specific
keys to GWY. GWY reads back as all zeros. The WUT supports the following independent, software keyed commands:
â–º Cancel all posted and executing write transactions in the WUT with immediate effect.
â–º Capture a sticky snapshot of the CNT1, CNT0, and CNT2 MMRs into SNAP1, SNAP0, and SNAP2.
Table 387. Bit Descriptions for GWY
Bits Bit Name Settings Description Reset Access
[15:0] SWKEY Software Keyed Command Issued by the CPU. This register is the write target for activating software keyed
commands issued by the CPU to the WUT. Supported keys are FLUSH_RTC and SNAPSHOT_RTC.
FLUSH_RTC is a software key of Value 0xA2C5 delivered via a register write to GWY. FLUSH_RTC
causes the WUT to flush all posted write transactions and to immediately stop any transaction that it is
currently executing. The CPU only uses this key when power loss to the core is imminent and the CPU
wants to cleanly and quickly terminate communication activity across the power domain boundary before
the always on half of the WUT activates its isolation barrier. SNAPSHOT_RTC is a key of Value 0x7627
delivered via a register write to GWY. SNAPSHOT_RTC causes the WUT to take a sticky snapshot of the
value of CNT1, CNT0, and CNT2 and store it in SNAP1, SNAP0, and SNAP2. Snapshots are sticky until a
new one is requested.
0x0 W
CONTROL 1 REGISTER
Address: 0x40001428, Reset: 0x01E0, Name: CR1
This register is a secondary control register that expands the level of WUT control, which is provided by CR0.
CR1 allows additional sticky interrupt sources in SR2 to be enabled. These sources fan into the WUT peripheral interrupt to optionally tell the
CPU when the WUT count has changed, when a prescaled (modulo 1) gated clock event has occurred to advance the WUT count, when a trim
boundary has occurred, when the 32-bit WUT count in CNT1 or CNT0 has rolled over, and when the modulo 60 version of the WUT count has
rolled over.
Table 388. Bit Descriptions for CR1
Bits Bit Name Settings Description Reset Access
[15:9] Reserved Reserved. 0x0 R
[8:5] PRESCALE2EXP Prescale Power of Two Division Factor for the WUT Base Clock. PRESCALE2EXP
defines the power of two by which the WUT base clock (nominally 32 kHz) is prescaled
before being used to count time by advancing the contents of the CNT1 and CNT0
0xF R/W
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